preserve-emulation/pcsx2
1
0 Fork 0
mirror of https://github.com/PCSX2/pcsx2.git synced 2026-11-13 01:30:29 +01:00
Code Issues Packages Projects Releases Wiki Activity

interpreter: fix a subtle bug in a QFSRV

Browse Source 
Math is correct but a shift of 64 bits is illegal in x86 because the cl register is masked

From the x86 spec:
    The destination operand can be a register or a memory location. The count operand can be an immediate value or
    the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is
    limited to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding is provided for a count of 1.
This commit is contained in:
Gregory Hainaut committed 2016-01-12 19:29:10 +01:00
1 parent 22de865582
commit 46a2f6ed24
1 file changed
+6 -2
Download Patch File Download Diff File Expand all files Collapse all files
pcsx2/MMI.cpp
+6 -2
View File
@@ -1032,8 +1032,12 @@ void QFSRV() { // JayteeMaster: changed a bit to avoid screw up
*/
Rd.UD[0] = cpuRegs.GPR.r[_Rt_].UD[1] >> (sa_amt - 64);
Rd.UD[1] = cpuRegs.GPR.r[_Rs_].UD[0] >> (sa_amt - 64);
Rd.UD[0]|= cpuRegs.GPR.r[_Rs_].UD[0] << (128 - sa_amt);
Rd.UD[1]|= cpuRegs.GPR.r[_Rs_].UD[1] << (128 - sa_amt);
if (sa_amt != 64) {
// A 64 bit shift is equivalent to a 0 bit shift because value is masked
// on 6 bits
Rd.UD[0]|= cpuRegs.GPR.r[_Rs_].UD[0] << (128u - sa_amt);
Rd.UD[1]|= cpuRegs.GPR.r[_Rs_].UD[1] << (128u - sa_amt);
}
cpuRegs.GPR.r[_Rd_] = Rd;
}
}