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Common: Switch CVT instructions to auto SSE/AVX
This commit is contained in:
TellowKrinkle
committed by
TellowKrinkle
TellowKrinkle
parent
de022ab68d
commit
23918e25c2
@@ -565,15 +565,23 @@ namespace x86Emitter
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extern void xCVTSD2SI(const xRegister32or64& to, const xRegisterSSE& from);
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extern void xCVTSD2SI(const xRegister32or64& to, const xIndirect64& from);
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extern void xCVTSD2SS(const xRegisterSSE& to, const xRegisterSSE& from);
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extern void xCVTSD2SS(const xRegisterSSE& to, const xIndirect64& from);
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extern void xCVTSI2SS(const xRegisterSSE& to, const xRegister32or64& from);
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extern void xCVTSI2SS(const xRegisterSSE& to, const xIndirect32& from);
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extern void xCVTSD2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2);
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extern void xCVTSD2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect64& src2);
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extern void xCVTSI2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegister32or64& src2);
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extern void xCVTSI2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect32& src2);
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extern void xCVTSI2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect64& src2);
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static void xCVTSD2SS(const xRegisterSSE& to, const xRegisterSSE& from) { xCVTSD2SS(to, to, from); }
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static void xCVTSD2SS(const xRegisterSSE& to, const xIndirect64& from) { xCVTSD2SS(to, to, from); }
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static void xCVTSI2SS(const xRegisterSSE& to, const xRegister32or64& from) { xCVTSI2SS(to, to, from); }
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static void xCVTSI2SS(const xRegisterSSE& to, const xIndirect32& from) { xCVTSI2SS(to, to, from); }
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static void xCVTSI2SS(const xRegisterSSE& to, const xIndirect64& from) { xCVTSI2SS(to, to, from); }
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extern void xCVTSS2SD(const xRegisterSSE& to, const xRegisterSSE& from);
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extern void xCVTSS2SD(const xRegisterSSE& to, const xIndirect32& from);
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extern void xCVTSS2SI(const xRegister32or64& to, const xRegisterSSE& from);
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extern void xCVTSS2SI(const xRegister32or64& to, const xIndirect32& from);
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extern void xCVTSS2SD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2);
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extern void xCVTSS2SD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect32& src2);
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static void xCVTSS2SD(const xRegisterSSE& to, const xRegisterSSE& from) { xCVTSS2SD(to, to, from); }
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static void xCVTSS2SD(const xRegisterSSE& to, const xIndirect32& from) { xCVTSS2SD(to, to, from); }
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extern void xCVTTPD2DQ(const xRegisterSSE& to, const xRegisterSSE& from);
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extern void xCVTTPD2DQ(const xRegisterSSE& to, const xIndirect128& from);
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+33
-32
@@ -229,45 +229,46 @@ namespace x86Emitter
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// nature of the functions. (so if a function expects an m32, you must use (u32*) or ptr32[]).
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//
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__fi void xCVTDQ2PD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0xe6); }
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__fi void xCVTDQ2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0xf3, 0xe6); }
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__fi void xCVTDQ2PS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x00, 0x5b); }
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__fi void xCVTDQ2PS(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x00, 0x5b); }
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__fi void xCVTDQ2PD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0xe6).pf3()); }
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__fi void xCVTDQ2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0xe6).pf3()); }
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__fi void xCVTDQ2PS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5b)); }
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__fi void xCVTDQ2PS(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5b)); }
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__fi void xCVTPD2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0xe6); }
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__fi void xCVTPD2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0xf2, 0xe6); }
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__fi void xCVTPD2PS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x66, 0x5a); }
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__fi void xCVTPD2PS(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x66, 0x5a); }
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__fi void xCVTPD2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0xe6).pf2()); }
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__fi void xCVTPD2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0xe6).pf2()); }
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__fi void xCVTPD2PS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5a).p66()); }
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__fi void xCVTPD2PS(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5a).p66()); }
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__fi void xCVTPI2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0x66, 0x2a); }
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__fi void xCVTPI2PS(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0x00, 0x2a); }
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__fi void xCVTPI2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2a).p66()); }
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__fi void xCVTPI2PS(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2a)); }
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__fi void xCVTPS2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x66, 0x5b); }
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__fi void xCVTPS2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x66, 0x5b); }
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__fi void xCVTPS2PD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x00, 0x5a); }
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__fi void xCVTPS2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0x00, 0x5a); }
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__fi void xCVTPS2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5b).p66()); }
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__fi void xCVTPS2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5b).p66()); }
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__fi void xCVTPS2PD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5a)); }
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__fi void xCVTPS2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5a)); }
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__fi void xCVTSD2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0x2d); }
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__fi void xCVTSD2SI(const xRegister32or64& to, const xIndirect64& from) { OpWriteSSE(0xf2, 0x2d); }
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__fi void xCVTSD2SS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0x5a); }
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__fi void xCVTSD2SS(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0xf2, 0x5a); }
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__fi void xCVTSI2SS(const xRegisterSSE& to, const xRegister32or64& from) { OpWriteSSE(0xf3, 0x2a); }
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__fi void xCVTSI2SS(const xRegisterSSE& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x2a); }
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__fi void xCVTSD2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2d).dstw().pf2()); }
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__fi void xCVTSD2SI(const xRegister32or64& to, const xIndirect64& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2d).dstw().pf2()); }
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__fi void xCVTSD2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) { EmitSIMD(SIMDInstructionInfo(0x5a).pf2(), dst, src1, src2); }
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__fi void xCVTSD2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect64& src2) { EmitSIMD(SIMDInstructionInfo(0x5a).pf2(), dst, src1, src2); }
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__fi void xCVTSI2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegister32or64& src2) { EmitSIMD(SIMDInstructionInfo(0x2a).srcw().pf3(), dst, src1, src2); }
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__fi void xCVTSI2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect32& src2) { EmitSIMD(SIMDInstructionInfo(0x2a).srcw().pf3(), dst, src1, src2); }
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__fi void xCVTSI2SS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect64& src2) { EmitSIMD(SIMDInstructionInfo(0x2a).srcw().pf3(), dst, src1, src2); }
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__fi void xCVTSS2SD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x5a); }
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__fi void xCVTSS2SD(const xRegisterSSE& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x5a); }
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__fi void xCVTSS2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x2d); }
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__fi void xCVTSS2SI(const xRegister32or64& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x2d); }
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__fi void xCVTSS2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2d).dstw().pf3()); }
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__fi void xCVTSS2SI(const xRegister32or64& to, const xIndirect32& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2d).dstw().pf3()); }
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__fi void xCVTSS2SD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) { EmitSIMD(SIMDInstructionInfo(0x5a).pf3(), dst, src1, src2); }
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__fi void xCVTSS2SD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirect32& src2) { EmitSIMD(SIMDInstructionInfo(0x5a).pf3(), dst, src1, src2); }
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__fi void xCVTTPD2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x66, 0xe6); }
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__fi void xCVTTPD2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x66, 0xe6); }
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__fi void xCVTTPS2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x5b); }
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__fi void xCVTTPS2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0xf3, 0x5b); }
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__fi void xCVTTPD2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0xe6).p66()); }
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__fi void xCVTTPD2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0xe6).p66()); }
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__fi void xCVTTPS2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5b).pf3()); }
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__fi void xCVTTPS2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x5b).pf3()); }
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__fi void xCVTTSD2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0x2c); }
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__fi void xCVTTSD2SI(const xRegister32or64& to, const xIndirect64& from) { OpWriteSSE(0xf2, 0x2c); }
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__fi void xCVTTSS2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x2c); }
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__fi void xCVTTSS2SI(const xRegister32or64& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x2c); }
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__fi void xCVTTSD2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2c).dstw().pf2()); }
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__fi void xCVTTSD2SI(const xRegister32or64& to, const xIndirect64& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2c).dstw().pf2()); }
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__fi void xCVTTSS2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2c).dstw().pf3()); }
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__fi void xCVTTSS2SI(const xRegister32or64& to, const xIndirect32& from) { OpWriteSIMDMovOp(SIMDInstructionInfo(0x2c).dstw().pf3()); }
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// ------------------------------------------------------------------------
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@@ -147,6 +147,27 @@ TEST(CodegenTests, JmpTest)
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TEST(CodegenTests, SSETest)
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{
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x86Emitter::use_avx = false;
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CODEGEN_TEST(xCVTDQ2PD(xmm0, ptr64[rax]), "f3 0f e6 00");
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CODEGEN_TEST(xCVTDQ2PS(xmm0, xmm8), "41 0f 5b c0");
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CODEGEN_TEST(xCVTPD2DQ(xmm8, ptr128[r8]), "f2 45 0f e6 00");
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CODEGEN_TEST(xCVTPD2PS(xmm1, xmm7), "66 0f 5a cf");
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CODEGEN_TEST(xCVTSD2SI(rax, xmm1), "f2 48 0f 2d c1");
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CODEGEN_TEST(xCVTSD2SI(esi, ptr64[rax]), "f2 0f 2d 30");
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CODEGEN_TEST(xCVTSD2SS(xmm3, xmm4), "f2 0f 5a dc");
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CODEGEN_TEST(xCVTSI2SS(xmm8, ecx), "f3 44 0f 2a c1");
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CODEGEN_TEST(xCVTSI2SS(xmm3, ptr32[r8]), "f3 41 0f 2a 18");
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CODEGEN_TEST(xCVTSI2SS(xmm3, ptr64[r8]), "f3 49 0f 2a 18");
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CODEGEN_TEST(xCVTSS2SD(xmm8, xmm7), "f3 44 0f 5a c7");
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CODEGEN_TEST(xCVTSS2SD(xmm4, ptr32[rcx]), "f3 0f 5a 21");
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CODEGEN_TEST(xCVTSS2SI(eax, xmm4), "f3 0f 2d c4");
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CODEGEN_TEST(xCVTSS2SI(rcx, ptr32[rax]), "f3 48 0f 2d 08");
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CODEGEN_TEST(xCVTTPD2DQ(xmm4, xmm7), "66 0f e6 e7");
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CODEGEN_TEST(xCVTTPS2DQ(xmm5, xmm3), "f3 0f 5b eb");
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CODEGEN_TEST(xCVTTSD2SI(rdx, xmm4), "f2 48 0f 2c d4");
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CODEGEN_TEST(xCVTTSS2SI(ecx, xmm3), "f3 0f 2c cb");
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CODEGEN_TEST(xMOVAPS(xmm0, xmm1), "0f 28 c1");
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CODEGEN_TEST(xMOVAPS(xmm8, xmm9), "45 0f 28 c1");
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CODEGEN_TEST(xMOVUPS(xmm8, ptr128[r8+r9]), "47 0f 10 04 08");
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@@ -175,6 +196,27 @@ TEST(CodegenTests, SSETest)
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TEST(CodegenTests, AVXTest)
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{
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x86Emitter::use_avx = true;
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CODEGEN_TEST(xCVTDQ2PD(xmm0, ptr64[rax]), "c5 fa e6 00");
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CODEGEN_TEST(xCVTDQ2PS(xmm0, xmm8), "c4 c1 78 5b c0");
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CODEGEN_TEST(xCVTPD2DQ(xmm8, ptr128[r8]), "c4 41 7b e6 00");
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CODEGEN_TEST(xCVTPD2PS(xmm1, xmm7), "c5 f9 5a cf");
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CODEGEN_TEST(xCVTSD2SI(rax, xmm1), "c4 e1 fb 2d c1");
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CODEGEN_TEST(xCVTSD2SI(esi, ptr64[rax]), "c5 fb 2d 30");
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CODEGEN_TEST(xCVTSD2SS(xmm3, xmm4), "c5 e3 5a dc");
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CODEGEN_TEST(xCVTSI2SS(xmm8, ecx), "c5 3a 2a c1");
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CODEGEN_TEST(xCVTSI2SS(xmm3, ptr32[r8]), "c4 c1 62 2a 18");
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CODEGEN_TEST(xCVTSI2SS(xmm3, ptr64[r8]), "c4 c1 e2 2a 18");
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CODEGEN_TEST(xCVTSS2SD(xmm8, xmm7), "c5 3a 5a c7");
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CODEGEN_TEST(xCVTSS2SD(xmm4, ptr32[rcx]), "c5 da 5a 21");
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CODEGEN_TEST(xCVTSS2SI(eax, xmm4), "c5 fa 2d c4");
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CODEGEN_TEST(xCVTSS2SI(rcx, ptr32[rax]), "c4 e1 fa 2d 08");
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CODEGEN_TEST(xCVTTPD2DQ(xmm4, xmm7), "c5 f9 e6 e7");
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CODEGEN_TEST(xCVTTPS2DQ(xmm5, xmm3), "c5 fa 5b eb");
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CODEGEN_TEST(xCVTTSD2SI(rdx, xmm4), "c4 e1 fb 2c d4");
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CODEGEN_TEST(xCVTTSS2SI(ecx, xmm3), "c5 fa 2c cb");
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CODEGEN_TEST(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
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CODEGEN_TEST(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
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CODEGEN_TEST(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");
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@@ -226,6 +268,8 @@ TEST(CodegenTests, AVXTest)
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TEST(CodegenTests, AVX256Test)
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{
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x86Emitter::use_avx = true;
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CODEGEN_TEST(xVMOVAPS(ymm0, ymm1), "c5 fc 28 c1");
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CODEGEN_TEST(xVMOVAPS(ymm0, ptr32[rdi]), "c5 fc 28 07");
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CODEGEN_TEST(xVMOVAPS(ptr32[rdi], ymm0), "c5 fc 29 07");
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