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7 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 Rosalie Wanders
|
b78738e6ef | ||
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Rosalie Wanders
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9457552941 | ||
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Rosalie Wanders
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a322eb773c | ||
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Rosalie Wanders
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c9d83bd67b | ||
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Rosalie Wanders
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c8223edc9d | ||
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Rosalie Wanders
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ba24d0bc04 | ||
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Rosalie Wanders
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e3e04f3498 |
@@ -604,6 +604,7 @@ enum r4300_opcode r4300_decode(struct precomp_instr* inst, struct r4300_core* r4
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idec_u53(iw, idec->u53[0], &inst->f.cf.fd);
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switch(dummy)
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{
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case 0x10: inst->ops = cached_interp_CVT_S_S; return idec->opcode;
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case 0x11: inst->ops = cached_interp_CVT_S_D; return idec->opcode;
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case 0x14: inst->ops = cached_interp_CVT_S_W; return idec->opcode;
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case 0x15: inst->ops = cached_interp_CVT_S_L; return idec->opcode;
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+576
-222
File diff suppressed because it is too large
Load Diff
@@ -1553,8 +1553,17 @@ DECLARE_INSTRUCTION(CTC1)
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(*r4300_cp1_fcr31(&r4300->cp1)) = rrt32;
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update_x86_rounding_mode(&r4300->cp1);
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}
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//if (((*r4300_cp1_fcr31(&r4300->cp1)) >> 7) & 0x1F) printf("FPU Exception enabled : %x\n",
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// (int)(((*r4300_cp1_fcr31(&r4300->cp1)) >> 7) & 0x1F));
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//printf("CTC1 rtt32 = 0x%08X\n", rrt32);
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if (fpu_throw_exception(&rrt32))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1630,7 +1639,13 @@ DECLARE_INSTRUCTION(ABS_S)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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abs_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
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if (abs_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1638,7 +1653,13 @@ DECLARE_INSTRUCTION(ABS_D)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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abs_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
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if (abs_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1646,7 +1667,13 @@ DECLARE_INSTRUCTION(ADD_S)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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add_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
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if (add_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1654,7 +1681,13 @@ DECLARE_INSTRUCTION(ADD_D)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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add_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
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if (add_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1662,7 +1695,13 @@ DECLARE_INSTRUCTION(DIV_S)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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div_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
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if (div_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1670,7 +1709,13 @@ DECLARE_INSTRUCTION(DIV_D)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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div_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
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if (div_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1694,7 +1739,13 @@ DECLARE_INSTRUCTION(MUL_S)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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mul_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
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if (mul_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1702,7 +1753,13 @@ DECLARE_INSTRUCTION(MUL_D)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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mul_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
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if (mul_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1710,7 +1767,13 @@ DECLARE_INSTRUCTION(NEG_S)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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neg_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
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if (neg_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1718,7 +1781,13 @@ DECLARE_INSTRUCTION(NEG_D)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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neg_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
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if (neg_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1726,7 +1795,13 @@ DECLARE_INSTRUCTION(SQRT_S)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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sqrt_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
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if (sqrt_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
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{
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uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
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exception_general(r4300);
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return;
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}
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ADD_TO_PC(1);
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}
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@@ -1734,7 +1809,13 @@ DECLARE_INSTRUCTION(SQRT_D)
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{
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DECLARE_R4300
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if (check_cop1_unusable(r4300)) { return; }
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sqrt_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
|
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if (sqrt_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
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cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1742,7 +1823,13 @@ DECLARE_INSTRUCTION(SUB_S)
|
||||
{
|
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DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
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sub_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (sub_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1750,7 +1837,13 @@ DECLARE_INSTRUCTION(SUB_D)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
sub_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
|
||||
if (sub_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1758,7 +1851,13 @@ DECLARE_INSTRUCTION(TRUNC_W_S)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
trunc_w_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (trunc_w_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1790,7 +1889,13 @@ DECLARE_INSTRUCTION(ROUND_W_S)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
round_w_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (round_w_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1822,7 +1927,13 @@ DECLARE_INSTRUCTION(CEIL_W_S)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
ceil_w_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (ceil_w_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1882,11 +1993,29 @@ DECLARE_INSTRUCTION(FLOOR_L_D)
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(CVT_S_S)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
|
||||
*r4300_cp1_fcr31(&r4300->cp1) |= FCR31_CAUSE_UNIMPLOP_BIT;
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(CVT_S_D)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_s_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (cvt_s_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1894,7 +2023,13 @@ DECLARE_INSTRUCTION(CVT_S_W)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_s_w(r4300_cp1_fcr31(&r4300->cp1), (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (cvt_s_w(r4300_cp1_fcr31(&r4300->cp1), (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1902,7 +2037,13 @@ DECLARE_INSTRUCTION(CVT_S_L)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_s_l(r4300_cp1_fcr31(&r4300->cp1), (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (cvt_s_l(r4300_cp1_fcr31(&r4300->cp1), (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1910,15 +2051,39 @@ DECLARE_INSTRUCTION(CVT_D_S)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_d_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
|
||||
if (cvt_d_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(CVT_D_D)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
|
||||
*r4300_cp1_fcr31(&r4300->cp1) |= FCR31_CAUSE_UNIMPLOP_BIT;
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(CVT_D_W)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_d_w(r4300_cp1_fcr31(&r4300->cp1), (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
|
||||
if (cvt_d_w(r4300_cp1_fcr31(&r4300->cp1), (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1926,7 +2091,13 @@ DECLARE_INSTRUCTION(CVT_D_L)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_d_l(r4300_cp1_fcr31(&r4300->cp1), (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
|
||||
if (cvt_d_l(r4300_cp1_fcr31(&r4300->cp1), (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1934,7 +2105,13 @@ DECLARE_INSTRUCTION(CVT_W_S)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_w_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (cvt_w_s(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
@@ -1942,7 +2119,13 @@ DECLARE_INSTRUCTION(CVT_W_D)
|
||||
{
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
cvt_w_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
|
||||
if (cvt_w_d(r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]))
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_FPE;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
|
||||
@@ -525,6 +525,7 @@ void InterpretOpcode(struct r4300_core* r4300)
|
||||
case 13: TRUNC_W_S(r4300, op); break;
|
||||
case 14: CEIL_W_S(r4300, op); break;
|
||||
case 15: FLOOR_W_S(r4300, op); break;
|
||||
case 32: CVT_S_S(r4300, op); break;
|
||||
case 33: CVT_D_S(r4300, op); break;
|
||||
case 36: CVT_W_S(r4300, op); break;
|
||||
case 37: CVT_L_S(r4300, op); break;
|
||||
@@ -569,6 +570,7 @@ void InterpretOpcode(struct r4300_core* r4300)
|
||||
case 14: CEIL_W_D(r4300, op); break;
|
||||
case 15: FLOOR_W_D(r4300, op); break;
|
||||
case 32: CVT_S_D(r4300, op); break;
|
||||
case 33: CVT_D_D(r4300, op); break;
|
||||
case 36: CVT_W_D(r4300, op); break;
|
||||
case 37: CVT_L_D(r4300, op); break;
|
||||
case 48: C_F_D(r4300, op); break;
|
||||
@@ -621,18 +623,9 @@ void InterpretOpcode(struct r4300_core* r4300)
|
||||
break;
|
||||
case 18: /* Coprocessor 2 prefix */
|
||||
switch ((op >> 21) & 0x1F) {
|
||||
case 0: /* Coprocessor 2 opcode 0: MFC2 */
|
||||
if (RT_OF(op) != 0) MFC2(r4300, op);
|
||||
else NOP(r4300, 0);
|
||||
break;
|
||||
case 1: /* Coprocessor 2 opcode 1: DMFC2 */
|
||||
if (RT_OF(op) != 0) DMFC2(r4300, op);
|
||||
else NOP(r4300, 0);
|
||||
break;
|
||||
case 2: /* Coprocessor 2 opcode 2: CFC2 */
|
||||
if (RT_OF(op) != 0) CFC2(r4300, op);
|
||||
else NOP(r4300, 0);
|
||||
break;
|
||||
case 0: MFC2(r4300, op); break;
|
||||
case 1: DMFC2(r4300, op); break;
|
||||
case 2: CFC2(r4300, op); break;
|
||||
case 4: MTC2(r4300, op); break;
|
||||
case 5: DMTC2(r4300, op); break;
|
||||
case 6: CTC2(r4300, op); break;
|
||||
|
||||
Reference in New Issue
Block a user