mirror of
https://github.com/Rosalie241/RMG.git
synced 2026-07-11 01:24:01 +02:00
3rdParty: apply RSP fixes patch to mupen64plus-rsp-parallel
This commit is contained in:
Rosalie Wanders
+10
-29
@@ -20,8 +20,6 @@ RSP::CPU cpu;
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#else
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RSP::JIT::CPU cpu;
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#endif
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short MFC0_count[32];
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int SP_STATUS_TIMEOUT;
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} // namespace RSP
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extern "C"
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@@ -53,47 +51,33 @@ extern "C"
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EXPORT unsigned int CALL DoRspCycles(unsigned int cycles)
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{
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if (*RSP::rsp.SP_STATUS_REG & (SP_STATUS_HALT | SP_STATUS_BROKE))
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return 0;
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// We don't know if Mupen from the outside invalidated our IMEM.
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RSP::cpu.invalidate_imem();
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if (cycles)
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{
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RSP::cpu.get_state().last_instruction_type = RSP::VU_INSTRUCTION;
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RSP::cpu.get_state().instruction_pipeline = 0;
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RSP::cpu.invalidate_imem();
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}
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// Run CPU until we either break or we need to fire an IRQ.
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RSP::cpu.get_state().pc = *RSP::rsp.SP_PC_REG & 0xfff;
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RSP::cpu.get_state().instruction_count = 0;
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#ifdef INTENSE_DEBUG
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fprintf(stderr, "RUN TASK: %u\n", RSP::cpu.get_state().pc);
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log_rsp_mem_parallel();
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#endif
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for (auto &count : RSP::MFC0_count)
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count = 0;
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while (!(*RSP::rsp.SP_STATUS_REG & SP_STATUS_HALT))
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{
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auto mode = RSP::cpu.run();
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if (mode == RSP::MODE_CHECK_FLAGS && (*RSP::cpu.get_state().cp0.irq & 1))
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break;
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if (mode == RSP::MODE_EXIT)
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break;
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}
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*RSP::rsp.SP_PC_REG = 0x04001000 | (RSP::cpu.get_state().pc & 0xffc);
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// From CXD4.
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if (*RSP::rsp.SP_STATUS_REG & SP_STATUS_BROKE)
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return cycles;
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else if (*RSP::cpu.get_state().cp0.irq & 1)
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RSP::rsp.CheckInterrupts();
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else if (*RSP::rsp.SP_STATUS_REG & SP_STATUS_HALT)
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return cycles;
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else if (*RSP::rsp.SP_SEMAPHORE_REG != 0) // Semaphore lock fixes.
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{
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}
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else
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RSP::SP_STATUS_TIMEOUT = 16; // From now on, wait 16 times, not 0x7fff
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// CPU restarts with the correct SIGs.
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*RSP::rsp.SP_STATUS_REG &= ~SP_STATUS_HALT;
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*RSP::rsp.SP_PC_REG = (RSP::cpu.get_state().pc & 0xffc);
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return cycles;
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}
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@@ -157,9 +141,6 @@ extern "C"
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*cr[RSP::CP0_REGISTER_SP_STATUS] = SP_STATUS_HALT;
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RSP::cpu.get_state().cp0.irq = RSP::rsp.MI_INTR_REG;
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// From CXD4.
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RSP::SP_STATUS_TIMEOUT = 0x7fff;
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RSP::cpu.set_dmem(reinterpret_cast<uint32_t *>(Rsp_Info.DMEM));
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RSP::cpu.set_imem(reinterpret_cast<uint32_t *>(Rsp_Info.IMEM));
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RSP::cpu.set_rdram(reinterpret_cast<uint32_t *>(Rsp_Info.RDRAM));
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+130
-87
@@ -6,8 +6,6 @@
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namespace RSP
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{
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extern RSP_INFO rsp;
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extern short MFC0_count[32];
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extern int SP_STATUS_TIMEOUT;
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} // namespace RSP
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#endif
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@@ -28,34 +26,15 @@ extern "C"
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rsp->sr[rt] = res;
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#ifdef PARALLEL_INTEGRATION
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if (rd == CP0_REGISTER_SP_STATUS)
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{
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// Might be waiting for the CPU to set a signal bit on the STATUS register. Increment timeout
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RSP::MFC0_count[rt] += 1;
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if (RSP::MFC0_count[rt] >= RSP::SP_STATUS_TIMEOUT)
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{
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*RSP::rsp.SP_STATUS_REG |= SP_STATUS_HALT;
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return MODE_CHECK_FLAGS;
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}
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}
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#endif
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#if 0 // FIXME: this is broken with upstream mupen64plus-core
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if (rd == CP0_REGISTER_SP_SEMAPHORE)
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{
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if (*rsp->cp0.cr[CP0_REGISTER_SP_SEMAPHORE])
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{
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#ifdef PARALLEL_INTEGRATION
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RSP::MFC0_count[rt] += 8; // Almost certainly waiting on the CPU. Timeout faster.
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if (RSP::MFC0_count[rt] >= RSP::SP_STATUS_TIMEOUT)
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{
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*RSP::rsp.SP_STATUS_REG |= SP_STATUS_HALT;
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return MODE_CHECK_FLAGS;
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}
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#endif
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}
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else
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*rsp->cp0.cr[CP0_REGISTER_SP_SEMAPHORE] = 1;
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*rsp->cp0.cr[CP0_REGISTER_SP_SEMAPHORE] = 1;
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return MODE_EXIT;
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}
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// We don't return control to the CPU if the RDP FREEZE bit is set, doing so seems to cause flickering
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else if (rd == CP0_REGISTER_SP_STATUS && (*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] & DPC_STATUS_FREEZE) == 0)
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{
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return MODE_EXIT;
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}
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#endif
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@@ -65,12 +44,44 @@ extern "C"
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return MODE_CONTINUE;
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}
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#define RSP_HANDLE_STATUS_WRITE(flag) \
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switch (rt & (SP_SET_##flag | SP_CLR_##flag)) \
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{ \
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case SP_SET_##flag: status |= SP_STATUS_##flag; break; \
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case SP_CLR_##flag: status &= ~SP_STATUS_##flag; break; \
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default: break; \
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static inline void rdp_status_write(RSP::CPUState *rsp, uint32_t rt)
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{
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uint32_t status = *rsp->cp0.cr[CP0_REGISTER_CMD_STATUS];
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if (rt & DPC_CLR_XBUS_DMEM_DMA)
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status &= ~DPC_STATUS_XBUS_DMEM_DMA;
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else if (rt & DPC_SET_XBUS_DMEM_DMA)
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status |= DPC_STATUS_XBUS_DMEM_DMA;
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if (rt & DPC_CLR_FREEZE)
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status &= ~DPC_STATUS_FREEZE;
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else if (rt & DPC_SET_FREEZE)
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status |= DPC_STATUS_FREEZE;
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if (rt & DPC_CLR_FLUSH)
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status &= ~DPC_STATUS_FLUSH;
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else if (rt & DPC_SET_FLUSH)
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status |= DPC_STATUS_FLUSH;
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if (rt & DPC_CLR_TMEM_CTR)
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{
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status &= ~DPC_STATUS_TMEM_BUSY;
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*rsp->cp0.cr[CP0_REGISTER_CMD_TMEM_BUSY] = 0;
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}
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if (rt & DPC_CLR_PIPE_CTR)
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{
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status &= ~DPC_STATUS_PIPE_BUSY;
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*rsp->cp0.cr[CP0_REGISTER_CMD_PIPE_BUSY] = 0;
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}
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if (rt & DPC_CLR_CMD_CTR)
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{
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status &= ~DPC_STATUS_CMD_BUSY;
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*rsp->cp0.cr[CP0_REGISTER_CMD_BUSY] = 0;
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}
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if (rt & DPC_CLR_CLOCK_CTR)
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*rsp->cp0.cr[CP0_REGISTER_CMD_CLOCK] = 0;
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] = status;
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}
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static inline int rsp_status_write(RSP::CPUState *rsp, uint32_t rt)
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@@ -79,28 +90,69 @@ extern "C"
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uint32_t status = *rsp->cp0.cr[CP0_REGISTER_SP_STATUS];
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RSP_HANDLE_STATUS_WRITE(HALT)
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RSP_HANDLE_STATUS_WRITE(SSTEP)
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RSP_HANDLE_STATUS_WRITE(INTR_BREAK)
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RSP_HANDLE_STATUS_WRITE(SIG0)
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RSP_HANDLE_STATUS_WRITE(SIG1)
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RSP_HANDLE_STATUS_WRITE(SIG2)
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RSP_HANDLE_STATUS_WRITE(SIG3)
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RSP_HANDLE_STATUS_WRITE(SIG4)
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RSP_HANDLE_STATUS_WRITE(SIG5)
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RSP_HANDLE_STATUS_WRITE(SIG6)
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RSP_HANDLE_STATUS_WRITE(SIG7)
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switch (rt & (SP_SET_INTR | SP_CLR_INTR))
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{
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case SP_SET_INTR: *rsp->cp0.irq |= 1; break;
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case SP_CLR_INTR: *rsp->cp0.irq &= ~1; break;
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default: break;
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}
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if ((rt & SP_CLR_HALT) && !(rt & SP_SET_HALT))
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status &= ~SP_STATUS_HALT;
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if ((rt & SP_SET_HALT) && !(rt & SP_CLR_HALT))
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status |= SP_STATUS_HALT;
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if (rt & SP_CLR_BROKE)
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status &= ~SP_STATUS_BROKE;
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if ((rt & SP_CLR_INTR) && !(rt & SP_SET_INTR))
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*rsp->cp0.irq &= ~1;
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if ((rt & SP_SET_INTR) && !(rt & SP_CLR_INTR))
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*rsp->cp0.irq |= 1;
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if ((rt & SP_CLR_SSTEP) && !(rt & SP_SET_SSTEP))
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status &= ~SP_STATUS_SSTEP;
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if ((rt & SP_SET_SSTEP) && !(rt & SP_CLR_SSTEP))
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status |= SP_STATUS_SSTEP;
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if ((rt & SP_CLR_INTR_BREAK) && !(rt & SP_SET_INTR_BREAK))
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status &= ~SP_STATUS_INTR_BREAK;
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if ((rt & SP_SET_INTR_BREAK) && !(rt & SP_CLR_INTR_BREAK))
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status |= SP_STATUS_INTR_BREAK;
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if ((rt & SP_CLR_SIG0) && !(rt & SP_SET_SIG0))
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status &= ~SP_STATUS_SIG0;
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if ((rt & SP_SET_SIG0) && !(rt & SP_CLR_SIG0))
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status |= SP_STATUS_SIG0;
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if ((rt & SP_CLR_SIG1) && !(rt & SP_SET_SIG1))
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status &= ~SP_STATUS_SIG1;
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if ((rt & SP_SET_SIG1) && !(rt & SP_CLR_SIG1))
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status |= SP_STATUS_SIG1;
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if ((rt & SP_CLR_SIG2) && !(rt & SP_SET_SIG2))
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status &= ~SP_STATUS_SIG2;
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if ((rt & SP_SET_SIG2) && !(rt & SP_CLR_SIG2))
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status |= SP_STATUS_SIG2;
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if ((rt & SP_CLR_SIG3) && !(rt & SP_SET_SIG3))
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status &= ~SP_STATUS_SIG3;
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if ((rt & SP_SET_SIG3) && !(rt & SP_CLR_SIG3))
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status |= SP_STATUS_SIG3;
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if ((rt & SP_CLR_SIG4) && !(rt & SP_SET_SIG4))
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status &= ~SP_STATUS_SIG4;
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if ((rt & SP_SET_SIG4) && !(rt & SP_CLR_SIG4))
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status |= SP_STATUS_SIG4;
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if ((rt & SP_CLR_SIG5) && !(rt & SP_SET_SIG5))
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status &= ~SP_STATUS_SIG5;
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if ((rt & SP_SET_SIG5) && !(rt & SP_CLR_SIG5))
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status |= SP_STATUS_SIG5;
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if ((rt & SP_CLR_SIG6) && !(rt & SP_SET_SIG6))
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status &= ~SP_STATUS_SIG6;
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if ((rt & SP_SET_SIG6) && !(rt & SP_CLR_SIG6))
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status |= SP_STATUS_SIG6;
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if ((rt & SP_CLR_SIG7) && !(rt & SP_SET_SIG7))
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status &= ~SP_STATUS_SIG7;
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if ((rt & SP_SET_SIG7) && !(rt & SP_CLR_SIG7))
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status |= SP_STATUS_SIG7;
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*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] = status;
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return ((*rsp->cp0.irq & 1) || (status & SP_STATUS_HALT)) ? MODE_CHECK_FLAGS : MODE_CONTINUE;
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}
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@@ -109,14 +161,9 @@ extern "C"
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static int rsp_dma_read(RSP::CPUState *rsp)
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{
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uint32_t length_reg = *rsp->cp0.cr[CP0_REGISTER_DMA_READ_LENGTH];
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uint32_t length = (length_reg & 0xFFF) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFFF;
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unsigned count = (length_reg >> 12) & 0xFF;
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// Force alignment.
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length = (length + 0x7) & ~0x7;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] &= ~0x3;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] &= ~0x7;
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uint32_t length = ((length_reg & 0xFFF) | 7) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFF8;
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unsigned count = ((length_reg >> 12) & 0xFF) + 1;
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// Check length.
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if (((*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF) + length) > 0x1000)
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@@ -156,7 +203,7 @@ extern "C"
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source += length + skip;
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dest += length;
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} while (++i <= count);
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} while (++i < count);
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = source;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = dest;
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@@ -171,14 +218,9 @@ extern "C"
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static void rsp_dma_write(RSP::CPUState *rsp)
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{
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uint32_t length_reg = *rsp->cp0.cr[CP0_REGISTER_DMA_WRITE_LENGTH];
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uint32_t length = (length_reg & 0xFFF) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFFF;
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unsigned count = (length_reg >> 12) & 0xFF;
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// Force alignment.
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length = (length + 0x7) & ~0x7;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] &= ~0x3;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] &= ~0x7;
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uint32_t length = ((length_reg & 0xFFF) | 7) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFF8;
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unsigned count = ((length_reg >> 12) & 0xFF) + 1;
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// Check length.
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if (((*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF) + length) > 0x1000)
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@@ -210,7 +252,7 @@ extern "C"
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source += length;
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dest += length + skip;
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} while (++i <= count);
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} while (++i < count);
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = source;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = dest;
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@@ -228,11 +270,11 @@ extern "C"
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switch (static_cast<CP0Registers>(rd & 15))
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{
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case CP0_REGISTER_DMA_CACHE:
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = val & 0x1fff;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = val & 0x1ff8;
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break;
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case CP0_REGISTER_DMA_DRAM:
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = val & 0xffffff;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = val & 0xfffff8;
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break;
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case CP0_REGISTER_DMA_READ_LENGTH:
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@@ -254,26 +296,34 @@ extern "C"
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return rsp_status_write(rsp, val);
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case CP0_REGISTER_SP_SEMAPHORE:
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// Any write to the semaphore register, regardless of value, sets it to 0 for the next read
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*rsp->cp0.cr[CP0_REGISTER_SP_SEMAPHORE] = 0;
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break;
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case CP0_REGISTER_CMD_START:
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#ifdef INTENSE_DEBUG
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fprintf(stderr, "CMD_START 0x%x\n", val & 0xfffffff8u);
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fprintf(stderr, "CMD_START 0x%x\n", val & 0xfffff8u);
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#endif
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*rsp->cp0.cr[CP0_REGISTER_CMD_START] = *rsp->cp0.cr[CP0_REGISTER_CMD_CURRENT] =
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*rsp->cp0.cr[CP0_REGISTER_CMD_END] = val & 0xfffffff8u;
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if (!(*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] & DPC_STATUS_START_VALID))
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{
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*rsp->cp0.cr[CP0_REGISTER_CMD_START] = val & 0xfffff8u;
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}
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] |= DPC_STATUS_START_VALID;
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break;
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case CP0_REGISTER_CMD_END:
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#ifdef INTENSE_DEBUG
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fprintf(stderr, "CMD_END 0x%x\n", val & 0xfffffff8u);
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fprintf(stderr, "CMD_END 0x%x\n", val & 0xfffff8u);
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#endif
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*rsp->cp0.cr[CP0_REGISTER_CMD_END] = val & 0xfffffff8u;
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*rsp->cp0.cr[CP0_REGISTER_CMD_END] = val & 0xfffff8u;
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if (*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] & DPC_STATUS_START_VALID)
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{
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*rsp->cp0.cr[CP0_REGISTER_CMD_CURRENT] = *rsp->cp0.cr[CP0_REGISTER_CMD_START];
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] &= ~DPC_STATUS_START_VALID;
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}
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#ifdef PARALLEL_INTEGRATION
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RSP::rsp.ProcessRdpList();
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if (*rsp->cp0.irq & 0x20)
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return MODE_EXIT;
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#endif
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break;
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@@ -282,14 +332,7 @@ extern "C"
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break;
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case CP0_REGISTER_CMD_STATUS:
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] &= ~(!!(val & 0x1) << 0);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] |= (!!(val & 0x2) << 0);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] &= ~(!!(val & 0x4) << 1);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] |= (!!(val & 0x8) << 1);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] &= ~(!!(val & 0x10) << 2);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] |= (!!(val & 0x20) << 2);
|
||||
*rsp->cp0.cr[CP0_REGISTER_CMD_TMEM_BUSY] &= !(val & 0x40) * -1;
|
||||
*rsp->cp0.cr[CP0_REGISTER_CMD_CLOCK] &= !(val & 0x200) * -1;
|
||||
rdp_status_write(rsp, val);
|
||||
break;
|
||||
|
||||
case CP0_REGISTER_CMD_CURRENT:
|
||||
|
||||
+1
-2
@@ -1927,14 +1927,13 @@ ReturnMode CPU::run()
|
||||
{
|
||||
case MODE_BREAK:
|
||||
*state.cp0.cr[CP0_REGISTER_SP_STATUS] |= SP_STATUS_BROKE | SP_STATUS_HALT;
|
||||
if (*state.cp0.cr[CP0_REGISTER_SP_STATUS] & SP_STATUS_INTR_BREAK)
|
||||
*state.cp0.irq |= 1;
|
||||
#ifndef PARALLEL_INTEGRATION
|
||||
print_registers();
|
||||
#endif
|
||||
return MODE_BREAK;
|
||||
|
||||
case MODE_CHECK_FLAGS:
|
||||
case MODE_EXIT:
|
||||
case MODE_DMA_READ:
|
||||
return static_cast<ReturnMode>(ret);
|
||||
|
||||
|
||||
+36
-1
@@ -48,6 +48,31 @@ enum CP0Registers
|
||||
CP0_REGISTER_CMD_TMEM_BUSY = 15,
|
||||
};
|
||||
|
||||
// CMD_STATUS read bits.
|
||||
#define DPC_STATUS_XBUS_DMEM_DMA 0x001
|
||||
#define DPC_STATUS_FREEZE 0x002
|
||||
#define DPC_STATUS_FLUSH 0x004
|
||||
#define DPC_STATUS_START_GCLK 0x008
|
||||
#define DPC_STATUS_TMEM_BUSY 0x010
|
||||
#define DPC_STATUS_PIPE_BUSY 0x020
|
||||
#define DPC_STATUS_CMD_BUSY 0x040
|
||||
#define DPC_STATUS_CBUF_READY 0x080
|
||||
#define DPC_STATUS_DMA_BUSY 0x100
|
||||
#define DPC_STATUS_END_VALID 0x200
|
||||
#define DPC_STATUS_START_VALID 0x400
|
||||
|
||||
// CMD_STATUS write bits.
|
||||
#define DPC_CLR_XBUS_DMEM_DMA 0x001
|
||||
#define DPC_SET_XBUS_DMEM_DMA 0x002
|
||||
#define DPC_CLR_FREEZE 0x004
|
||||
#define DPC_SET_FREEZE 0x008
|
||||
#define DPC_CLR_FLUSH 0x010
|
||||
#define DPC_SET_FLUSH 0x020
|
||||
#define DPC_CLR_TMEM_CTR 0x040
|
||||
#define DPC_CLR_PIPE_CTR 0x080
|
||||
#define DPC_CLR_CMD_CTR 0x100
|
||||
#define DPC_CLR_CLOCK_CTR 0x200
|
||||
|
||||
// SP_STATUS read bits.
|
||||
#define SP_STATUS_HALT 0x0001
|
||||
#define SP_STATUS_BROKE 0x0002
|
||||
@@ -117,6 +142,9 @@ struct alignas(64) CP2
|
||||
struct CPUState
|
||||
{
|
||||
uint32_t pc = 0;
|
||||
uint32_t instruction_count = 0;
|
||||
uint32_t last_instruction_type = 0;
|
||||
uint32_t instruction_pipeline = 0;
|
||||
uint32_t dirty_blocks = 0;
|
||||
static_assert(CODE_BLOCKS <= 32, "Code blocks must fit in 32-bit register.");
|
||||
|
||||
@@ -138,7 +166,14 @@ enum ReturnMode
|
||||
MODE_CONTINUE = 1,
|
||||
MODE_BREAK = 2,
|
||||
MODE_DMA_READ = 3,
|
||||
MODE_CHECK_FLAGS = 4
|
||||
MODE_CHECK_FLAGS = 4,
|
||||
MODE_EXIT = 5
|
||||
};
|
||||
|
||||
enum InstructionType
|
||||
{
|
||||
VU_INSTRUCTION = 0,
|
||||
SU_INSTRUCTION = 1
|
||||
};
|
||||
|
||||
} // namespace RSP
|
||||
|
||||
Reference in New Issue
Block a user