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xenia/src/xenia/gpu/d3d12/shaders/dxbc/fullscreen_tc_vs.txt
T
Triang3l 913e1e949c [GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
2021-04-26 22:12:09 +03:00

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//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_VertexID 0 x 0 VERTID uint x
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// TEXCOORD 0 xy 0 NONE float xy
// SV_Position 0 xyzw 1 POS float xyzw
//
vs_5_1
dcl_globalFlags refactoringAllowed
dcl_input_sgv v0.x, vertex_id
dcl_output o0.xy
dcl_output_siv o1.xyzw, position
dcl_temps 1
ishl r0.y, v0.x, l(1)
mov r0.x, v0.x
and r0.xy, r0.xyxx, l(2, 2, 0, 0)
utof r0.xy, r0.xyxx
mad o1.xy, r0.xyxx, l(2.000000, -2.000000, 0.000000, 0.000000), l(-1.000000, 1.000000, 0.000000, 0.000000)
mov o1.zw, l(0,0,0,1.000000)
mov o0.xy, r0.xyxx
ret
// Approximately 8 instruction slots used