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Moving disasm to new tables.
Also adding useful CPU docs.
This commit is contained in:
Ben Vanik
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2006/09/01 Revision 1.2
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-----------------------------------------------------------------
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This is a description of the VMX128-type opcodes found on
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the xbox360 processor. I figured this out by looking at
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various disassmblies, so there might some errors and
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missing instructions. Some instructions have unknown
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semantics for me.
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See comments or corrections to sb#biallas.net
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=================================================================
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Conventions:
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VD128, VS128: 5 lower bits of a VMX128 vector register
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number
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VDh: upper 2 bits of VD128
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(so register number is (VDh << 5 | VD128))
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VA128: same as VD128
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A: bit 6 of VA128
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a: bit 5 of VA128
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(so register number is (A<<6 | a<<5 | VA128))
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VB128: same as VD128
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VBh: same as VDh
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VC128: 3 bits of a VMX128 vector register number
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(you can only use vr0-vr7 here)
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RA, RB: general purpose register number
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UIMM: unsigned immediate value
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SIMM: signed immediate value
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PERMh: upper 3 bits of a permutation
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PERMl: lower 5 bits of a permutation
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x, y, z: unknown immediate values
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=================================================================
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lvewx128 Load Vector128 Element Word Indexed
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|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 1 0 0 0|VDh|1 1|
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lvewx128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvlx128 Load Vector128 Left Indexed
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|0 0 0 1 0 0| VD128 | RA | RB |1 0 0 0 0 0 0|VDh|1 1|
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lvlx128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvrx128 Load Vector128 Right Indexed
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|0 0 0 1 0 0| VD128 | RA | RB |1 0 0 0 1 0 0|VDh|1 1|
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lvrx128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvlxl128 Load Vector128 Left Indexed LRU
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|0 0 0 1 0 0| VD128 | RA | RB |1 1 0 0 0 0 0|VDh|1 1|
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lvlxl128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvrxl128 Load Vector128 Right Indexed LRU
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|0 0 0 1 0 0| VD128 | RA | RB |1 1 0 0 1 0 0|VDh|1 1|
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lvrxl128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvsl128 Load Vector128 for Shift Left
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|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 0 0 0 0|VDh|1 1|
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lvsl128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvsr128 Load Vector128 for Shift Right
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|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 0 1 0 0|VDh|1 1|
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lvsr128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvx128 Load Vector128 Indexed
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|0 0 0 1 0 0| VD128 | RA | RB |0 0 0 1 1 0 0|VDh|1 1|
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lvx128 vr(VD128), r(RA), r(RB)
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=================================================================
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lvxl128 Load Vector128 Indexed LRU
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|0 0 0 1 0 0| VD128 | RA | RB |0 1 0 1 1 0 0|VDh|1 1|
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lvxl128 vr(VD128), r(RA), r(RB)
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=================================================================
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stewx128 Store Vector128 Element Word Indexed
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|0 0 0 1 0 0| VS128 | RA | RB |0 1 1 0 0 0 0|VDh|1 1|
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stvewx128 vr(VS128), r(RA), r(RB)
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=================================================================
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stvlx128 Store Vector128 Left Indexed
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|0 0 0 1 0 0| VS128 | RA | RB |1 0 1 0 0 0 0|VDh|1 1|
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stvlx128 vr(VS128), r(RA), r(RB)
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=================================================================
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stvlxl128 Store Vector128 Left Indexed LRU
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|0 0 0 1 0 0| VS128 | RA | RB |1 1 1 0 0 0 0|VDh|1 1|
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lvlxl128 vr(VS128), r(RA), r(RB)
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=================================================================
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stvrx128 Store Vector128 Right Indexed
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|0 0 0 1 0 0| VS128 | RA | RB |1 0 1 0 1 0 0|VDh|1 1|
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stvrx128 vr(VS128), r(RA), r(RB)
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=================================================================
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stvrxl128 Store Vector128 Right Indexed LRU
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|0 0 0 1 0 0| VS128 | RA | RB |1 1 1 0 1 0 0|VDh|1 1|
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stvrxl128 vr(VS128), r(RA), r(RB)
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=================================================================
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stvx128 Store Vector128 Indexed
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|0 0 0 1 0 0| VS128 | RA | RB |0 0 1 1 1 0 0|VDh|1 1|
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stvx128 vr(VS128), r(RA), r(RB)
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=================================================================
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stvxl128 Store Vector128 Indexed LRU
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|0 0 0 1 0 0| VS128 | RA | RB |0 1 1 1 1 0 0|VDh|1 1|
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stvxl128 vr(VS128), r(RA), r(RB)
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=================================================================
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vaddfp128 Vector128 Add Floating Point
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 0|a|1|VDh|VBh|
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vaddfp128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vand128 Vector128 Logical AND
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 0|a|1|VDh|VBh|
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vand128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vandc128 Vector128 Logical AND
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with Complement
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|1|VDh|VBh|
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vandc128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vcfpsxws128 Vector128 Convert From Floating-Point to
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Signed Fixed-Point Word Saturate
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|0 0 0 1 1 0| VD128 | SIMM | VB128 |0 1 0 0 0 1 1|VDh|VBh|
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vcfpsxws128 vr(VD128), vr(VB128), SIMM
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=================================================================
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vcfpuxws128 Vector128 Convert From Floating-Point to
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Unsigned Fixed-Point Word Saturate
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|0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 0 1 1 1|VDh|VBh|
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vcfpuxws128 vr(VD128), vr(VB128), UIMM
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=================================================================
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vcmpbfp128 Vector128 Compare Bounds
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Floating Point
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 1|R|a|0|VDh|VBh|
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vcmpbfp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
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vcmpbfp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
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=================================================================
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vcmpeqfp128 Vector128 Compare Equal-to
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Floating Point
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 0|R|a|0|VDh|VBh|
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vcmpeqfp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
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vcmpeqfp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
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=================================================================
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vcmpequw128 Vector128 Compare Equal-to
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Unsigned Word
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 0|R|a|0|VDh|VBh|
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vcmpequw128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
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vcmpequw128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
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=================================================================
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vcmpgefp128 Vector128 Compare Greater-Than-
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or-Equal-to Floating Point
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 1|R|a|0|VDh|VBh|
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vcmpgefp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
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vcmpgefp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
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=================================================================
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vcmpgtfp128 Vector128 Compare Greater-Than
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Floating-Point
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 0|R|a|0|VDh|VBh|
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vcmpgtfp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
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vcmpgtfp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
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=================================================================
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vcsxwfp128 Vector128 Convert From Signed Fixed-Point
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Word to Floating-Point
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|0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 1 0 1 1|VDh|VBh|
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vcsxwfp128 vr(VD128), vr(VB128), SIMM
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=================================================================
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vcuxwfp128 Vector128 Convert From Unsigned Fixed-Point
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Word to Floating-Point
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|0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 1 1 1 1|VDh|VBh|
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vcuxwfp128 vr(VD128), vr(VB128), UIMM
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=================================================================
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vexptefp128 Vector128 2 Raised to the Exponent
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Estimate Floating Point
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|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 1 0 1 1|VDh|VBh|
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vexptefp128 vr(VD128), vr(VB128)
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=================================================================
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vlogefp128 Vector128 Log2 Estimate
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Floating Point
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|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 1 1 1 1|VDh|VBh|
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vlogefp128 vr(VD128), vr(VB128)
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=================================================================
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vmaddcfp128 Vector128 Multiply Add
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Floating Point
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|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 1 0 0|a|1|VDh|VBh|
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vmaddcfp128 vr(VDS128), vr(VA128), vr(VSD128), vr(VB128)
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=================================================================
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vmaddfp128 Vector128 Multiply Add
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Floating Point
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|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 0 1 1|a|1|VDh|VBh|
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vmaddfp128 vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
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=================================================================
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vmaxfp128 Vector128 Maximum
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Floating Point
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 1 0|a|0|VDh|VBh|
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vmaxfp128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vminfp128 Vector128 Minimum
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Floating Point
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 1 1|a|0|VDh|VBh|
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vminfp128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vmrghw128 Vector128 Merge High Word
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 0 0|a|0|VDh|VBh|
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vmrghw128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vmrglw128 Vector128 Merge Low Word
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|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 0 1|a|0|VDh|VBh|
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vmrglw128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vmsum3fp128 Vector128 Multiply Sum 3-way
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Floating Point
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 1 1 0|a|1|VDh|VBh|
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vmsub3fp128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vmsum4fp128 Vector128 Multiply Sum 4-way
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Floating-Point
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 1 1 1|a|1|VDh|VBh|
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vmsub4fp128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vmulfp128 Vector128 Multiply
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Floating-Point
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 1 0|a|1|VDh|VBh|
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vmulfp128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vnmsubfp128 Vector128 Negative Multiply-Subtract
|
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Floating Point
|
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|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 1 0 1|a|1|VDh|VBh|
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vnmsubfp128 vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
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=================================================================
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vnor128 Vector128 Logical NOR
|
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|1|VDh|VBh|
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vnor128 vr(VD128), vr(VA128), vr(VB128)
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=================================================================
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vor128 Vector128 Logical OR
|
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|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 1|a|1|VDh|VBh|
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vor128 vr(VD128), vr(VA128), vr(VB128)
|
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=================================================================
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vperm128 Vector128 Permutation
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0| VC |a|0|VDh|VBh|
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vperm128 vr(VD128), vr(VA128), vr(VB128), vr(VC)
|
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=================================================================
|
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vpermwi128 Vector128 Permutate Word Immediate
|
||||
|0 0 0 1 1 0| VD128 | PERMl | VB128 |0|1|PERMh|0|1|VDh|VBh|
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|
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vpermwi128 vr(VD128), vr(VB128), (PERMh << 5 | PERMl)
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=================================================================
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vpkd3d128 Vector128 Pack D3Dtype, Rotate Left
|
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Immediate and Mask Insert
|
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|0 0 0 1 1 0| VD128 | x | y | VB128 |1 1 0| z |0 1|VDh|VBh|
|
||||
|
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vpkd3d128 vr(VD128), vr(VB128), x, y, z
|
||||
|
||||
|
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=================================================================
|
||||
vpkshss128 Vector128 Pack Signed Half Word
|
||||
Signed Saturate
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 0|a|0|VDh|VBh|
|
||||
|
||||
vpkshss128 vr(VD128), vr(VA128), vr(VB128)
|
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|
||||
|
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=================================================================
|
||||
vpkshus128 Vector128 Pack Signed Half Word
|
||||
Unsigned Saturate
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 1|a|0|VDh|VBh|
|
||||
|
||||
vpkshus128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vpkswss128 Vector128 Pack Signed Word
|
||||
Signed Saturate
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|0|VDh|VBh|
|
||||
|
||||
vpkswss128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vpkswus128 Vector128 Pack Signed Word
|
||||
Unsigned Saturate
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 1|a|0|VDh|VBh|
|
||||
|
||||
vpkswus128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vpkuhum128 Vector128 Pack Unsigned Half Word
|
||||
Unsigned Modulo
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 0|a|0|VDh|VBh|
|
||||
|
||||
vpkuhum128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vpkuhus128 Vector128 Pack Unsigned Half Word
|
||||
Unsigned Saturate
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 1|a|0|VDh|VBh|
|
||||
|
||||
vpkuhus128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vpkuwum128 Vector128 Pack Unsigned Word
|
||||
Unsigned Modulo
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 0|a|0|VDh|VBh|
|
||||
|
||||
vpkuwum128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vpkuwus128 Vector128 Pack Unsigned Word
|
||||
Unsigned Saturate
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 1|a|0|VDh|VBh|
|
||||
|
||||
vpkuwus128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vrefp128 Vector128 Reciprocal Estimate
|
||||
Floating Point
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 0 0 1 1|VDh|VBh|
|
||||
|
||||
vrefp128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vrfim128 Vector128 Round to Floating-Point
|
||||
Integer toward -oo
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 0 0 1 1|VDh|VBh|
|
||||
|
||||
vrfim128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vrfin128 Vector128 Round to Floating-Point
|
||||
Integer toward Nearest
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 0 1 1 1|VDh|VBh|
|
||||
|
||||
vrfin128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vrfip128 Vector128 Round to Floating-Point
|
||||
Integer toward +oo
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 0 1 1|VDh|VBh|
|
||||
|
||||
vrfip128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vrfiz128 Vector128 Round to Floating-Point
|
||||
Integer toward Zero
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 1 1 1|VDh|VBh|
|
||||
|
||||
vrfiz128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vrlimi128 Vector128 Rotate Left Immediate
|
||||
and Mask Insert
|
||||
|0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1| z |0 1|VDh|VBh|
|
||||
|
||||
vrlimi128 vr(VD128), vr(VB128), UIMM, z
|
||||
|
||||
|
||||
=================================================================
|
||||
vrlw128 Vector128 Rotate Left Word
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 1|a|1|VDh|VBh|
|
||||
|
||||
vrlw128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vrsqrtefp128 Vector128 Reciprocal Square Root
|
||||
Estimate Floating Point
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 0 1 1 1|VDh|VBh|
|
||||
|
||||
vrsqrtefp128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vsel128 Vector128 Select
|
||||
|0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|1 1 0 1|a|1|VDh|VBh|
|
||||
|
||||
vsel128 vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vsldoi128 Vector128 Shift Left Double
|
||||
by Octet Immediate
|
||||
|0 0 0 1 0 0| VD128 | VA128 | VB128 |A| SHB |a|1|VDh|VBh|
|
||||
|
||||
vsldoi128 vr(VD128), vr(VA128), vr(VB128), SHB
|
||||
|
||||
|
||||
=================================================================
|
||||
vslo128 Vector128 Shift Left Octet
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 0|a|1|VDh|VBh|
|
||||
|
||||
vslo128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vslw128 Vector128 Shift Left Word
|
||||
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 1 1|a|1|VDh|VBh|
|
||||
|
||||
vslw128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vspltisw128 Vector128 Splat Immediate
|
||||
Signed Word
|
||||
|0 0 0 1 1 0| VD128 | SIMM | VB128 |1 1 1 0 1 1 1|VDh|VBh|
|
||||
|
||||
vspltisw128 vr(VD128), vr(VB128), SIMM
|
||||
|
||||
|
||||
=================================================================
|
||||
vspltw128 Vector128 Splat Word
|
||||
|0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1 0 0 1 1|VDh|VBh|
|
||||
|
||||
vspltw128 vr(VD128), vr(VB128), UIMM
|
||||
|
||||
|
||||
=================================================================
|
||||
vsraw128 Vector128 Shift Right
|
||||
Arithmetic Word
|
||||
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 0 1|a|1|VDh|VBh|
|
||||
|
||||
vsraw128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vsro128 Vector128 Shift Right Octet
|
||||
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 1 1|a|1|VDh|VBh|
|
||||
|
||||
vsro128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vsrw128 Vector128 Shift Right Word
|
||||
|0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 1 1|a|1|VDh|VBh|
|
||||
|
||||
vsrw128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vsubfp128 Vector128 Subtract Floating Point
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 1|a|1|VDh|VBh|
|
||||
|
||||
vsubfp128 vr(VD128), vr(VA128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vupkd3d128 Vector128 Unpack D3Dtype
|
||||
|0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1 1 1 1 1|VDh|VBh|
|
||||
|
||||
vupkd3d128 vr(VD128), vr(VB128), UIMM
|
||||
|
||||
|
||||
=================================================================
|
||||
vupkhsb128 Vector128 Unpack
|
||||
High Signed Byte
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 0 0 0|VDh|VBh|
|
||||
|
||||
vupkhsb128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vupklsb128 Vector128 Unpack
|
||||
Low Signed Byte
|
||||
|0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 1 0 0|VDh|VBh|
|
||||
|
||||
vupkhsb128 vr(VD128), vr(VB128)
|
||||
|
||||
|
||||
=================================================================
|
||||
vxor128 Vector128 Logical XOR
|
||||
|0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 0|a|1|VDh|VBh|
|
||||
|
||||
vxor128 vr(VD128), vr(VA128), vr(VB128)
|
||||
Reference in New Issue
Block a user