//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeResolveConstants
// {
//
//   uint xe_resolve_edram_info;        // Offset:    0 Size:     4
//   uint xe_resolve_address_info;      // Offset:    4 Size:     4
//   uint xe_resolve_dest_info;         // Offset:    8 Size:     4
//   uint xe_resolve_dest_pitch;        // Offset:   12 Size:     4
//   uint xe_resolve_dest_base;         // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_resolve_source                 texture   uint2         buf      T0             t0      1 
// xe_resolve_dest                       UAV   uint4         buf      U0             u0      1 
// XeResolveConstants                cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 6
dcl_thread_group 8, 8, 1
ishl r0.xw, vThreadID.xxxx, l(2, 0, 0, 2)
ushr r1.x, CB0[0][0].y, l(7)
bfi r1.x, l(11), l(3), r1.x, l(0)
uge r1.x, r0.w, r1.x
if_nz r1.x
  ret 
endif 
ushr r1.xy, CB0[0][0].yyyy, l(5, 29, 0, 0)
mov r1.z, CB0[0][0].y
bfi r2.xy, l(5, 2, 0, 0), l(3, 3, 0, 0), r1.zxzz, l(0, 0, 0, 0)
mov r0.yz, vThreadID.yyyy
iadd r2.xy, r0.wzww, r2.xyxx
ubfe r1.w, l(12), l(13), CB0[0][0].x
and r3.xyzw, CB0[0][0].xzwz, l(1023, 0x01000000, 0x00003fff, 7)
uge r2.z, l(3), r1.y
if_nz r2.z
  mov r4.y, r1.y
else 
  ieq r2.z, r1.y, l(5)
  if_nz r2.z
    mov r4.y, l(2)
  else 
    mov r4.y, l(0)
  endif 
endif 
ishl r2.xz, r2.xxyx, l(1, 0, 1, 0)
ushr r4.x, r4.y, l(1)
bfi r2.xz, l(3, 0, 1, 0), l(0, 0, 0, 0), r4.xxyx, r2.xxzx
udiv r1.y, null, r2.x, l(80)
ubfe r2.y, l(28), l(3), r2.y
ishl r2.w, r1.y, l(1)
imad r2.w, r2.y, r3.x, r2.w
iadd r1.w, r1.w, r2.w
ineg r4.x, r1.y
ineg r4.y, r2.y
imad r2.xy, r4.xyxx, l(80, 16, 0, 0), r2.xzxx
imad r1.y, r2.y, l(80), r2.x
ishl r1.y, r1.y, l(1)
imad r1.y, r1.w, l(1280), r1.y
ushr r1.y, r1.y, l(1)
ld r2.xy, r1.yyyy, T0[0].xywz
iadd r4.xyz, r1.yyyy, l(2, 4, 6, 0)
ld r2.zw, r4.xxxx, T0[0].zwyx
ld r5.xy, r4.yyyy, T0[0].xywz
ld r5.zw, r4.zzzz, T0[0].zwyx
if_nz r3.y
  ubfe r1.y, l(6), l(7), CB0[0][0].z
  ieq r1.yw, r1.yyyy, l(0, 5, 0, 7)
  or r1.y, r1.w, r1.y
  if_nz r1.y
    mov r2.xyzw, r2.yxzw
    bfi r2.xyzw, l(16, 16, 16, 16), l(0, 0, 0, 0), r2.xywz, r2.yxzw
    mov r5.xyzw, r5.yxzw
    bfi r5.xyzw, l(16, 16, 16, 16), l(0, 0, 0, 0), r5.xywz, r5.yxzw
  endif 
endif 
bfi r1.xyzw, l(2, 2, 2, 2), l(3, 3, 3, 3), r1.zxxz, l(0, 0, 0, 0)
iadd r0.xyzw, r0.xyzw, r1.xyzw
and r1.x, CB0[0][0].z, l(8)
if_nz r1.x
  ubfe r3.xy, l(3, 14, 0, 0), l(4, 16, 0, 0), CB0[0][0].zwzz
  iadd r1.xy, r3.yzyy, l(31, 31, 0, 0)
  ishr r4.xyzw, r0.zwzw, l(4, 5, 3, 3)
  ishr r1.z, r3.x, l(2)
  ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
  and r1.x, r1.x, l(2046)
  imad r1.x, r1.z, r1.x, r4.x
  imad r1.x, r1.x, r1.y, r4.y
  ishl r1.y, r0.z, l(11)
  and r1.y, r1.y, l(0x00003000)
  bfi r1.y, l(3), l(9), r0.w, r1.y
  ishr r1.y, r1.y, l(6)
  iadd r1.z, r1.z, r4.z
  bfi r1.w, l(1), l(1), r1.z, l(0)
  iadd r1.w, r1.w, r4.w
  bfi r1.w, l(2), l(1), r1.w, l(0)
  bfi r1.z, l(1), l(0), r1.z, r1.w
  bfi r1.xw, l(19, 0, 0, 19), l(11, 0, 0, 14), r1.xxxx, l(0, 0, 0, 0)
  imad r1.xy, r1.yyyy, l(2, 16, 0, 0), r1.xwxx
  bfi r1.xy, l(2, 2, 0, 0), l(9, 12, 0, 0), r3.xxxx, r1.xyxx
  bfi r1.w, l(1), l(4), r0.z, l(0)
  ubfe r3.x, l(3), l(6), r1.x
  and r3.y, r1.z, l(6)
  bfi r1.z, l(1), l(8), r1.z, l(0)
  imad r1.z, r3.x, l(32), r1.z
  imad r1.z, r3.y, l(4), r1.z
  bfi r1.xy, l(6, 6, 0, 0), l(0, 3, 0, 0), r1.wwww, r1.xyxx
  bfi r1.y, l(9), l(3), r1.z, r1.y
  bfi r1.x, l(6), l(0), r1.x, r1.y
else 
  ishr r4.xyzw, r0.xyzw, l(5, 5, 2, 3)
  iadd r0.x, r3.z, l(31)
  ushr r0.x, r0.x, l(5)
  imad r0.x, r4.y, r0.x, r4.x
  ishl r1.yz, r0.zzzz, l(0, 6, 7, 0)
  and r1.yz, r1.yyzy, l(0, 896, 2048, 0)
  bfi r0.y, l(3), l(4), r0.w, r1.y
  bfi r0.y, l(22), l(10), r0.x, r0.y
  bfi r0.z, l(1), l(4), r0.z, l(0)
  iadd r0.y, r0.y, r0.z
  ishl r1.yw, r1.yyyy, l(0, 3, 0, 2)
  bfi r1.yw, l(0, 3, 0, 3), l(0, 7, 0, 6), r0.wwww, r1.yyyw
  bfi r0.xw, l(22, 0, 0, 22), l(13, 0, 0, 12), r0.xxxx, r1.yyyw
  imad r0.xz, r0.zzzz, l(8, 0, 4, 0), r0.xxwx
  bfi r0.x, l(12), l(0), r1.z, r0.x
  and r0.z, r0.z, l(1792)
  iadd r0.x, r0.x, r0.z
  and r0.z, r4.z, l(2)
  iadd r0.z, r4.w, r0.z
  bfi r0.z, l(2), l(6), r0.z, l(0)
  iadd r0.x, r0.x, r0.z
  bfi r1.x, l(6), l(0), r0.y, r0.x
endif 
iadd r0.x, r1.x, CB0[0][1].x
ushr r0.x, r0.x, l(4)
ieq r0.y, r3.w, l(4)
if_nz r0.y
  mov r2.xyzw, r2.yxwz
  mov r0.z, l(2)
else 
  mov r0.z, r3.w
endif 
ieq r1.xyz, r0.zzzz, l(1, 2, 3, 0)
or r0.zw, r1.yyyz, r1.xxxy
if_nz r0.z
  ishl r1.xyzw, r2.xywz, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r2.xywz, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r1.xywz, r4.xywz
endif 
if_nz r0.w
  ushr r1.xyzw, r2.xywz, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r1.xywz
endif 
store_uav_typed U0[0].xyzw, r0.xxxx, r2.xywz
iadd r0.x, r0.x, l(2)
if_nz r0.y
  mov r5.xyzw, r5.yxwz
  mov r3.w, l(2)
endif 
ieq r0.yzw, r3.wwww, l(0, 1, 2, 3)
or r0.yz, r0.zzwz, r0.yyzy
if_nz r0.y
  ishl r1.xyzw, r5.xywz, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r2.xyzw, r5.xywz, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r5.xyzw, r1.xywz, r2.xywz
endif 
if_nz r0.z
  ushr r1.xyzw, r5.xywz, l(16, 16, 16, 16)
  bfi r5.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r5.xyzw, r1.xywz
endif 
store_uav_typed U0[0].xyzw, r0.xxxx, r5.xywz
ret 
// Approximately 156 instruction slots used
