//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint xe_texture_load_host_base;    // Offset:    8 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   12 Size:     4
//   uint3 xe_texture_load_size_texels; // Offset:   16 Size:    12 [unused]
//   bool xe_texture_load_is_3d;        // Offset:   28 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   32 Size:    12
//   uint xe_texture_load_endianness;   // Offset:   44 Size:     4 [unused]
//   uint2 xe_texture_guest_storage_width_height;// Offset:   48 Size:     8
//   uint xe_texture_load_guest_format; // Offset:   56 Size:     4 [unused]
//   uint3 xe_texture_load_guest_mip_offset;// Offset:   64 Size:    12
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture    byte         r/o      T0             t0      1 
// xe_texture_load_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][5], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 9
dcl_thread_group 4, 16, 1
ishl r0.x, vThreadID.x, l(2)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][2].xyzx
or r0.w, r1.y, r1.x
or r0.w, r1.z, r0.w
if_nz r0.w
  ret 
endif 
iadd r0.xyz, r0.xyzx, CB0[0][4].xyzx
ieq r0.w, CB0[0][0].y, l(-1)
if_nz r0.w
  if_nz CB0[0][1].w
    iadd r1.xy, CB0[0][3].yxyy, l(31, 31, 0, 0)
    iadd r2.xyzw, r0.xxxx, l(0, 1, 2, 3)
    ushr r3.xyz, r0.yzyy, l(4, 2, 3, 0)
    ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
    and r0.w, r1.x, l(0x0ffffffe)
    imad r0.w, r3.y, r0.w, r3.x
    ushr r4.xyzw, r2.xyzw, l(5, 5, 5, 5)
    imad r1.xyzw, r0.wwww, r1.yyyy, r4.xyzw
    ishl r0.w, r0.y, l(2)
    and r0.w, r0.w, l(24)
    bfi r4.xyzw, l(3, 3, 3, 3), l(0, 0, 0, 0), r2.xyzw, r0.wwww
    iadd r0.w, r3.y, r3.z
    ushr r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
    bfi r3.x, l(1), l(1), r0.w, l(0)
    iadd r2.xyzw, r2.xyzw, r3.xxxx
    bfi r2.xyzw, l(2, 2, 2, 2), l(1, 1, 1, 1), r2.xyzw, l(0, 0, 0, 0)
    bfi r2.xyzw, l(1, 1, 1, 1), l(0, 0, 0, 0), r0.wwww, r2.xyzw
    and r3.xyzw, r4.xyzw, l(16, 16, 16, 16)
    bfi r5.xyzw, l(22, 22, 22, 22), l(8, 8, 8, 8), r1.xyzw, l(0, 0, 0, 0)
    imad r5.xyzw, r3.xyzw, l(2, 2, 2, 2), r5.xyzw
    bfi r5.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r4.xyzw, r5.xyzw
    bfi r5.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r0.zzzz, r5.xyzw
    bfi r6.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.yyyy, r5.xyzw
    ubfe r5.xyzw, l(3, 3, 3, 3), l(6, 6, 6, 6), r5.xyzw
    and r7.xyzw, r2.xyzw, l(6, 6, 6, 6)
    bfi r2.xyzw, l(1, 1, 1, 1), l(8, 8, 8, 8), r2.xyzw, l(0, 0, 0, 0)
    imad r2.xyzw, r5.xyzw, l(32, 32, 32, 32), r2.xyzw
    imad r2.xyzw, r7.xyzw, l(4, 4, 4, 4), r2.xyzw
    bfi r1.xyzw, l(22, 22, 22, 22), l(11, 11, 11, 11), r1.xyzw, l(0, 0, 0, 0)
    imad r1.xyzw, r3.xyzw, l(16, 16, 16, 16), r1.xyzw
    bfi r1.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r4.xyzw, r1.xyzw
    bfi r1.xyzw, l(2, 2, 2, 2), l(9, 9, 9, 9), r0.zzzz, r1.xyzw
    bfi r1.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.yyyy, r1.xyzw
    bfi r1.xyzw, l(9, 9, 9, 9), l(3, 3, 3, 3), r2.xyzw, r1.xyzw
    bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r6.xyzw, r1.xyzw
  else 
    iadd r2.xyzw, r0.xxxx, l(0, 1, 2, 3)
    ushr r3.xyzw, r2.xyzw, l(5, 5, 5, 5)
    ushr r4.xy, r0.yyyy, l(5, 2, 0, 0)
    iadd r0.w, CB0[0][3].x, l(31)
    ushr r0.w, r0.w, l(5)
    imad r3.xyzw, r4.xxxx, r0.wwww, r3.xyzw
    ishl r4.xz, r0.yyyy, l(2, 0, 7, 0)
    and r4.xz, r4.xxzx, l(56, 0, 2048, 0)
    bfi r5.xyzw, l(3, 3, 3, 3), l(0, 0, 0, 0), r2.xyzw, r4.xxxx
    ishl r0.w, r4.x, l(1)
    bfi r6.xyzw, l(3, 3, 3, 3), l(1, 1, 1, 1), r2.xyzw, r0.wwww
    and r6.xyzw, r6.xyzw, l(96, 96, 96, 96)
    bfi r7.xyzw, l(25, 25, 25, 25), l(7, 7, 7, 7), r3.xyzw, r6.xyzw
    bfi r7.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r5.xyzw, r7.xyzw
    bfi r7.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.yyyy, r7.xyzw
    ishl r8.xyzw, r6.xyzw, l(3, 3, 3, 3)
    bfi r8.xyzw, l(25, 25, 25, 25), l(10, 10, 10, 10), r3.xyzw, r8.xyzw
    bfi r8.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r5.xyzw, r8.xyzw
    bfi r8.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.yyyy, r8.xyzw
    bfi r8.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r4.zzzz, r8.xyzw
    ishl r6.xyzw, r6.xyzw, l(2, 2, 2, 2)
    bfi r3.xyzw, l(25, 25, 25, 25), l(9, 9, 9, 9), r3.xyzw, r6.xyzw
    bfi r3.xyzw, l(4, 4, 4, 4), l(2, 2, 2, 2), r5.xyzw, r3.xyzw
    bfi r3.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), r0.yyyy, r3.xyzw
    and r3.xyzw, r3.xyzw, l(1792, 1792, 1792, 1792)
    iadd r3.xyzw, r8.xyzw, r3.xyzw
    ushr r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
    and r0.w, r4.y, l(2)
    iadd r2.xyzw, r0.wwww, r2.xyzw
    bfi r2.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r2.xyzw, l(0, 0, 0, 0)
    iadd r2.xyzw, r3.xyzw, r2.xyzw
    bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r7.xyzw, r2.xyzw
  endif 
else 
  iadd r0.w, CB0[0][2].y, l(31)
  and r0.w, r0.w, l(-32)
  imad r0.y, r0.z, r0.w, r0.y
  imad r0.x, r0.y, CB0[0][0].y, r0.x
  iadd r1.xyzw, r0.xxxx, l(0, 1, 2, 3)
endif 
iadd r0.xyzw, r1.xyzw, CB0[0][0].xxxx
ishl r0.xyzw, r0.xyzw, l(2, 2, 2, 2)
ld_raw r1.x, r0.x, T0[0].xxxx
ld_raw r0.x, r0.y, T0[0].xxxx
ld_raw r1.y, r0.z, T0[0].xxxx
ld_raw r0.y, r0.w, T0[0].xxxx
ishl r0.zw, vThreadID.xxxy, l(0, 0, 3, 1)
ishl r1.z, CB0[0][2].y, l(1)
imad r0.w, vThreadID.z, r1.z, r0.w
imad r0.z, r0.w, CB0[0][0].w, r0.z
iadd r0.z, r0.z, CB0[0][0].z
bfi r1.zw, l(0, 0, 16, 16), l(0, 0, 16, 16), r0.xxxy, r1.xxxy
store_raw U0[0].xy, r0.z, r1.zwzz
iadd r0.z, r0.z, CB0[0][0].w
ushr r1.xy, r1.xyxx, l(16, 16, 0, 0)
bfi r0.xy, l(16, 16, 0, 0), l(0, 0, 0, 0), r1.xyxx, r0.xyxx
store_raw U0[0].xy, r0.z, r0.xyxx
ret 
// Approximately 106 instruction slots used
