//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Note: shader requires additional functionality:
//       UAVs at every shader stage
//
//
// Buffer Definitions: 
//
// cbuffer xe_system_cbuffer
// {
//
//   uint xe_flags;                     // Offset:    0 Size:     4
//   uint xe_line_loop_closing_index;   // Offset:    4 Size:     4 [unused]
//   uint xe_vertex_index_endian_and_edge_factors;// Offset:    8 Size:     4
//   int xe_vertex_base_index;          // Offset:   12 Size:     4
//   float4 xe_user_clip_planes[6];     // Offset:   16 Size:    96 [unused]
//   float3 xe_ndc_scale;               // Offset:  112 Size:    12 [unused]
//   uint xe_pixel_pos_reg;             // Offset:  124 Size:     4 [unused]
//   float3 xe_ndc_offset;              // Offset:  128 Size:    12 [unused]
//   float xe_pixel_half_pixel_offset;  // Offset:  140 Size:     4 [unused]
//   float2 xe_point_size;              // Offset:  144 Size:     8 [unused]
//   float2 xe_point_size_min_max;      // Offset:  152 Size:     8 [unused]
//   float2 xe_point_screen_to_ndc;     // Offset:  160 Size:     8 [unused]
//   uint2 xe_sample_count_log2;        // Offset:  168 Size:     8 [unused]
//   float xe_alpha_test_reference;     // Offset:  176 Size:     4 [unused]
//   uint xe_edram_resolution_square_scale;// Offset:  180 Size:     4 [unused]
//   uint xe_edram_pitch_tiles;         // Offset:  184 Size:     4 [unused]
//   uint xe_edram_depth_base_dwords;   // Offset:  188 Size:     4 [unused]
//   float4 xe_color_exp_bias;          // Offset:  192 Size:    16 [unused]
//   uint4 xe_color_output_map;         // Offset:  208 Size:    16 [unused]
//   float2 xe_tessellation_factor_range;// Offset:  224 Size:     8
//   float2 xe_edram_depth_range;       // Offset:  232 Size:     8 [unused]
//   float2 xe_edram_poly_offset_front; // Offset:  240 Size:     8 [unused]
//   float2 xe_edram_poly_offset_back;  // Offset:  248 Size:     8 [unused]
//   uint4 xe_edram_stencil[2];         // Offset:  256 Size:    32 [unused]
//   uint4 xe_edram_rt_base_dwords_scaled;// Offset:  288 Size:    16 [unused]
//   uint4 xe_edram_rt_format_flags;    // Offset:  304 Size:    16 [unused]
//   float4 xe_edram_rt_clamp[4];       // Offset:  320 Size:    64 [unused]
//   uint4 xe_edram_rt_keep_mask[2];    // Offset:  384 Size:    32 [unused]
//   uint4 xe_edram_rt_blend_factors_ops;// Offset:  416 Size:    16 [unused]
//   float4 xe_edram_blend_constant;    // Offset:  432 Size:    16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_shared_memory_srv              texture    byte         r/o      T0             t0      1 
// xe_shared_memory_uav                  UAV    byte         r/w      U0             u0      1 
// xe_system_cbuffer                 cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Patch Constant signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_TessFactor            0   x           0  TRIEDGE   float   x   
// SV_TessFactor            1   x           1  TRIEDGE   float   x   
// SV_TessFactor            2   x           2  TRIEDGE   float   x   
// SV_InsideTessFactor      0   x           3   TRIINT   float   x   
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
// Tessellation Domain   # of control points
// -------------------- --------------------
// Triangle                                3
//
// Tessellation Output Primitive  Partitioning Type 
// ------------------------------ ------------------
// Clockwise Triangles            Even Fractional   
//
hs_5_1
hs_decls 
dcl_input_control_point_count 3
dcl_output_control_point_count 3
dcl_tessellator_domain domain_tri
dcl_tessellator_partitioning partitioning_fractional_even
dcl_tessellator_output_primitive output_triangle_cw
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][15], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
hs_fork_phase 
dcl_input vPrim
dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor
dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor
dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor
dcl_temps 3
imul null, r0.x, CB0[0][0].w, l(3)
imad r0.x, vPrim, l(3), r0.x
and r0.yzw, CB0[0][0].zzxz, l(0, 0x1ffffffc, 1, 2)
ishl r0.x, r0.x, l(2)
iadd r0.x, r0.x, r0.y
if_nz r0.z
  ld_raw r1.xyz, r0.x, U0[0].xyzx
else 
  ld_raw r1.xyz, r0.x, T0[0].xyzx
endif 
ushr r0.x, CB0[0][0].z, l(1)
xor r0.x, r0.x, CB0[0][0].z
and r0.x, r0.x, l(1)
if_nz r0.x
  ishl r0.xyz, r1.xyzx, l(8, 8, 8, 0)
  and r0.xyz, r0.xyzx, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0)
  ushr r2.xyz, r1.xyzx, l(8, 8, 8, 0)
  and r2.xyz, r2.xyzx, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0)
  iadd r1.xyz, r0.xyzx, r2.xyzx
endif 
if_nz r0.w
  ushr r0.xyz, r1.xyzx, l(16, 16, 16, 0)
  bfi r1.xyz, l(16, 16, 16, 0), l(16, 16, 16, 0), r1.xyzx, r0.xyzx
endif 
add r0.xyz, r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
max r0.xyz, r0.xyzx, CB0[0][14].xxxx
min r0.xyz, r0.xyzx, CB0[0][14].yyyy
mov o0.x, r0.z
mov o1.x, r0.y
mov o2.x, r0.x
ret 
hs_join_phase 
dcl_input vpc0.x
dcl_input vpc1.x
dcl_input vpc2.x
dcl_output_siv o3.x, finalTriInsideTessFactor
dcl_temps 1
min r0.x, vpc0.x, vpc1.x
min o3.x, r0.x, vpc2.x
ret 
// Approximately 34 instruction slots used
