//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_samples_2x_depth_pitch;// Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 6
dcl_thread_group 40, 16, 1
and r0.x, CB0[0][1].x, l(2047)
ushr r0.y, CB0[0][1].x, l(16)
imad r0.x, vThreadGroupID.y, r0.y, r0.x
ishl r0.y, vThreadGroupID.x, l(1)
iadd r0.x, r0.y, r0.x
imul null, r0.y, vThreadIDInGroup.y, l(640)
imad r0.x, r0.x, l(5120), r0.y
ishl r0.y, vThreadIDInGroup.x, l(4)
iadd r0.x, r0.y, r0.x
ubfe r0.yzw, l(0, 1, 1, 1), l(0, 13, 12, 11), CB0[0][1].xxxx
ishl r0.y, r0.y, l(1)
ishl r0.x, r0.x, r0.y
iadd r1.xyz, r0.xxxx, l(16, 32, 48, 0)
ld_raw r2.xyzw, r0.x, T0[0].zwxy
ld_raw r3.xyzw, r1.x, T0[0].zwxy
ld_raw r4.xyzw, r1.y, T0[0].xyzw
ld_raw r1.xyzw, r1.z, T0[0].xyzw
if_nz r0.z
  mov r0.xy, r4.xyxx
  mov r5.xy, r1.xyxx
  mov r4.xy, r2.xyxx
  mov r1.xy, r3.xyxx
  mov r2.xy, r0.xyxx
  mov r3.xy, r5.xyxx
endif 
not r0.x, r0.w
and r0.xy, r0.xwxx, vThreadID.yyyy
imad r0.x, r0.x, l(2), r0.y
ishl r0.y, vThreadID.x, l(5)
imad r0.x, r0.x, CB0[0][0].y, r0.y
store_raw U0[0].xyzw, r0.x, r2.zwxy
iadd r0.y, r0.x, l(16)
store_raw U0[0].xyzw, r0.y, r4.xyzw
ishl r0.y, l(1), r0.w
imad r0.x, r0.y, CB0[0][0].y, r0.x
store_raw U0[0].xyzw, r0.x, r3.zwxy
iadd r0.y, r0.x, l(16)
store_raw U0[0].xyzw, r0.y, r1.xyzw
ret 
// Approximately 39 instruction slots used
