//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint2 xe_texture_load_guest_storage_width_height;// Offset:    8 Size:     8
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_is_3d_endian; // Offset:   28 Size:     4
//   uint xe_texture_load_host_base;    // Offset:   32 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   36 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   40 Size:     4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint4         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 10
dcl_thread_group 4, 32, 1
ishl r0.x, vThreadID.x, l(3)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][1].xyzx
or r0.z, r1.y, r1.x
or r0.z, r1.z, r0.z
if_nz r0.z
  ret 
endif 
ishl r0.yz, r0.xxyx, l(0, 1, 1, 0)
ishl r0.w, CB0[0][1].y, l(1)
ishl r0.y, r0.y, l(2)
imad r0.z, vThreadID.z, r0.w, r0.z
imad r0.y, r0.z, CB0[0][2].y, r0.y
iadd r0.y, r0.y, CB0[0][2].x
ushr r0.z, CB0[0][2].y, l(4)
ieq r0.w, CB0[0][0].y, l(-1)
if_nz r0.w
  and r1.x, CB0[0][1].w, l(1)
  if_nz r1.x
    iadd r1.xy, CB0[0][0].wzww, l(31, 31, 0, 0)
    ishr r2.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
    and r1.x, r1.x, l(0x0ffffffe)
    imad r1.x, r2.y, r1.x, r2.x
    ibfe r1.zw, l(0, 0, 27, 29), l(0, 0, 2, 0), vThreadID.xxxx
    imad r1.x, r1.x, r1.y, r1.z
    ishl r1.y, vThreadID.y, l(10)
    ishr r1.y, r1.y, l(6)
    and r1.y, r1.y, l(96)
    iadd r1.z, r2.y, r2.z
    bfi r2.x, l(1), l(1), r1.z, l(0)
    iadd r1.w, r1.w, r2.x
    bfi r1.w, l(2), l(1), r1.w, l(0)
    bfi r1.z, l(1), l(0), r1.z, r1.w
    bfi r1.xw, l(20, 0, 0, 20), l(10, 0, 0, 13), r1.xxxx, l(0, 0, 0, 0)
    imad r1.xy, r1.yyyy, l(2, 16, 0, 0), r1.xwxx
    bfi r1.xy, l(2, 2, 0, 0), l(8, 11, 0, 0), vThreadID.zzzz, r1.xyxx
    bfi r1.w, l(1), l(4), vThreadID.y, l(0)
    ubfe r2.x, l(3), l(6), r1.x
    and r2.y, r1.z, l(6)
    bfi r1.z, l(1), l(8), r1.z, l(0)
    imad r1.z, r2.x, l(32), r1.z
    imad r1.z, r2.y, l(4), r1.z
    bfi r1.xy, l(6, 6, 0, 0), l(0, 3, 0, 0), r1.wwww, r1.xyxx
    bfi r1.y, l(9), l(3), r1.z, r1.y
    bfi r1.x, l(6), l(0), r1.x, r1.y
  else 
    ibfe r1.yz, l(0, 27, 29, 0), l(0, 2, 0, 0), vThreadID.xxxx
    ishr r2.xy, vThreadID.yyyy, l(5, 2, 0, 0)
    iadd r1.w, CB0[0][0].z, l(31)
    ushr r1.w, r1.w, l(5)
    imad r1.y, r2.x, r1.w, r1.y
    ishl r2.xz, vThreadID.yyyy, l(5, 0, 7, 0)
    and r2.xz, r2.xxzx, l(448, 0, 2048, 0)
    bfi r1.w, l(23), l(9), r1.y, r2.x
    bfi r2.w, l(1), l(4), vThreadID.y, l(0)
    iadd r1.w, r1.w, r2.w
    ishl r3.xy, r2.xxxx, l(3, 2, 0, 0)
    bfi r3.xy, l(23, 23, 0, 0), l(12, 11, 0, 0), r1.yyyy, r3.xyxx
    imad r2.xw, r2.wwww, l(8, 0, 0, 4), r3.xxxy
    bfi r1.y, l(12), l(0), r2.z, r2.x
    and r2.x, r2.w, l(1792)
    iadd r1.y, r1.y, r2.x
    and r2.x, r2.y, l(2)
    iadd r1.z, r1.z, r2.x
    bfi r1.z, l(2), l(6), r1.z, l(0)
    iadd r1.y, r1.y, r1.z
    bfi r1.x, l(6), l(0), r1.w, r1.y
  endif 
else 
  ishl r0.x, r0.x, l(2)
  iadd r1.y, CB0[0][1].y, l(31)
  and r1.y, r1.y, l(-32)
  imad r1.y, vThreadID.z, r1.y, vThreadID.y
  imad r1.x, r1.y, CB0[0][0].y, r0.x
endif 
iadd r0.x, r1.x, CB0[0][0].x
ushr r0.xy, r0.xyxx, l(2, 4, 0, 0)
ushr r1.x, CB0[0][1].w, l(1)
ld r2.xyzw, r0.xxxx, T0[0].zwxy
ieq r1.xyz, r1.xxxx, l(1, 2, 3, 0)
or r1.xy, r1.yzyy, r1.xyxx
if_nz r1.x
  ishl r3.xyzw, r2.zwxy, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r2.zwxy, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r3.zwxy, r4.zwxy
endif 
if_nz r1.y
  ushr r3.xyzw, r2.zwxy, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r3.zwxy
  mov r3.xy, r2.zwzz
else 
  mov r3.xy, r2.zwzz
endif 
iadd r4.xyz, r0.xxxx, l(1, 2, 3, 0)
ld r5.xyzw, r4.xxxx, T0[0].xyzw
if_nz r1.x
  ishl r6.xyzw, r5.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r7.xyzw, r5.xyzw, l(8, 8, 8, 8)
  and r7.xyzw, r7.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r5.xyzw, r6.xyzw, r7.xyzw
endif 
if_nz r1.y
  ushr r6.xyzw, r5.xyzw, l(16, 16, 16, 16)
  bfi r6.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r5.xyzw, r6.xyzw
  mov r3.zw, r6.xxxy
  mov r2.zw, r6.zzzw
else 
  mov r3.zw, r5.xxxy
  mov r2.zw, r5.zzzw
endif 
ushr r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
ubfe r3.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r3.xyzw
ushr r6.xyzw, r5.xyzw, l(20, 20, 20, 20)
firstbit_hi r7.xyzw, r3.xyzw
iadd r7.xyzw, r7.xyzw, l(-11, -11, -11, -11)
movc r7.xyzw, r3.xyzw, r7.xyzw, l(21,21,21,21)
iadd r8.xyzw, -r7.xyzw, l(1, 1, 1, 1)
movc r8.xyzw, r6.xyzw, r6.xyzw, r8.xyzw
ishl r7.xyzw, r3.xyzw, r7.xyzw
and r7.xyzw, r7.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r3.xyzw, r6.xyzw, r3.xyzw, r7.xyzw
ishl r6.xyzw, r8.xyzw, l(23, 23, 23, 23)
iadd r6.xyzw, r6.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
iadd r3.xyzw, r6.xyzw, r3.xyzw
movc r3.xyzw, r5.xyzw, r3.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r0.yyyy, r3.xyzw
iadd r1.z, r0.z, r0.y
ushr r3.xyzw, r2.xyzw, l(8, 8, 8, 8)
ubfe r2.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r2.xyzw
ushr r5.xyzw, r3.xyzw, l(20, 20, 20, 20)
firstbit_hi r6.xyzw, r2.xyzw
iadd r6.xyzw, r6.xyzw, l(-11, -11, -11, -11)
movc r6.xyzw, r2.xyzw, r6.xyzw, l(21,21,21,21)
iadd r7.xyzw, -r6.xyzw, l(1, 1, 1, 1)
movc r7.xyzw, r5.xyzw, r5.xyzw, r7.xyzw
ishl r6.xyzw, r2.xyzw, r6.xyzw
and r6.xyzw, r6.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r2.xyzw, r5.xyzw, r2.xyzw, r6.xyzw
ishl r5.xyzw, r7.xyzw, l(23, 23, 23, 23)
iadd r5.xyzw, r5.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
iadd r2.xyzw, r5.xyzw, r2.xyzw
movc r2.xyzw, r3.xyzw, r2.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r1.zzzz, r2.xyzw
iadd r2.xyz, r0.yyyy, l(1, 2, 3, 0)
ld r3.xyzw, r4.yyyy, T0[0].zwxy
if_nz r1.x
  ishl r5.xyzw, r3.zwxy, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r3.zwxy, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r5.zwxy, r6.zwxy
endif 
if_nz r1.y
  ushr r5.xyzw, r3.zwxy, l(16, 16, 16, 16)
  bfi r3.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r5.zwxy
  mov r5.xy, r3.zwzz
else 
  mov r5.xy, r3.zwzz
endif 
ld r4.xyzw, r4.zzzz, T0[0].xyzw
if_nz r1.x
  ishl r6.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r7.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r7.xyzw, r7.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r4.xyzw, r6.xyzw, r7.xyzw
endif 
if_nz r1.y
  ushr r6.xyzw, r4.xyzw, l(16, 16, 16, 16)
  bfi r6.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r4.xyzw, r6.xyzw
  mov r5.zw, r6.xxxy
  mov r3.zw, r6.zzzw
else 
  mov r5.zw, r4.xxxy
  mov r3.zw, r4.zzzw
endif 
ushr r4.xyzw, r5.xyzw, l(8, 8, 8, 8)
ubfe r5.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r5.xyzw
ushr r6.xyzw, r4.xyzw, l(20, 20, 20, 20)
firstbit_hi r7.xyzw, r5.xyzw
iadd r7.xyzw, r7.xyzw, l(-11, -11, -11, -11)
movc r7.xyzw, r5.xyzw, r7.xyzw, l(21,21,21,21)
iadd r8.xyzw, -r7.xyzw, l(1, 1, 1, 1)
movc r8.xyzw, r6.xyzw, r6.xyzw, r8.xyzw
ishl r7.xyzw, r5.xyzw, r7.xyzw
and r7.xyzw, r7.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r5.xyzw, r6.xyzw, r5.xyzw, r7.xyzw
ishl r6.xyzw, r8.xyzw, l(23, 23, 23, 23)
iadd r6.xyzw, r6.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
iadd r5.xyzw, r6.xyzw, r5.xyzw
movc r4.xyzw, r4.xyzw, r5.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r2.xxxx, r4.xyzw
iadd r4.xyz, r0.zzzz, r2.xyzx
ushr r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
ubfe r3.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r3.xyzw
ushr r6.xyzw, r5.xyzw, l(20, 20, 20, 20)
firstbit_hi r7.xyzw, r3.xyzw
iadd r7.xyzw, r7.xyzw, l(-11, -11, -11, -11)
movc r7.xyzw, r3.xyzw, r7.xyzw, l(21,21,21,21)
iadd r8.xyzw, -r7.xyzw, l(1, 1, 1, 1)
movc r8.xyzw, r6.xyzw, r6.xyzw, r8.xyzw
ishl r7.xyzw, r3.xyzw, r7.xyzw
and r7.xyzw, r7.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r3.xyzw, r6.xyzw, r3.xyzw, r7.xyzw
ishl r6.xyzw, r8.xyzw, l(23, 23, 23, 23)
iadd r6.xyzw, r6.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
iadd r3.xyzw, r6.xyzw, r3.xyzw
movc r3.xyzw, r5.xyzw, r3.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r4.xxxx, r3.xyzw
if_nz r0.w
  iadd r0.y, r0.x, l(8)
else 
  iadd r0.y, r0.x, l(4)
endif 
ld r3.xyzw, r0.yyyy, T0[0].zwxy
if_nz r1.x
  ishl r5.xyzw, r3.zwxy, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r3.zwxy, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r5.zwxy, r6.zwxy
endif 
if_nz r1.y
  ushr r5.xyzw, r3.zwxy, l(16, 16, 16, 16)
  bfi r3.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r5.zwxy
  mov r5.xy, r3.zwzz
else 
  mov r5.xy, r3.zwzz
endif 
iadd r0.xyz, r0.yyyy, l(1, 2, 3, 0)
ld r6.xyzw, r0.xxxx, T0[0].xyzw
if_nz r1.x
  ishl r7.xyzw, r6.xyzw, l(8, 8, 8, 8)
  and r7.xyzw, r7.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r8.xyzw, r6.xyzw, l(8, 8, 8, 8)
  and r8.xyzw, r8.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r6.xyzw, r7.xyzw, r8.xyzw
endif 
if_nz r1.y
  ushr r7.xyzw, r6.xyzw, l(16, 16, 16, 16)
  bfi r7.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r6.xyzw, r7.xyzw
  mov r5.zw, r7.xxxy
  mov r3.zw, r7.zzzw
else 
  mov r5.zw, r6.xxxy
  mov r3.zw, r6.zzzw
endif 
ushr r6.xyzw, r5.xyzw, l(8, 8, 8, 8)
ubfe r5.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r5.xyzw
ushr r7.xyzw, r6.xyzw, l(20, 20, 20, 20)
firstbit_hi r8.xyzw, r5.xyzw
iadd r8.xyzw, r8.xyzw, l(-11, -11, -11, -11)
movc r8.xyzw, r5.xyzw, r8.xyzw, l(21,21,21,21)
iadd r9.xyzw, -r8.xyzw, l(1, 1, 1, 1)
movc r9.xyzw, r7.xyzw, r7.xyzw, r9.xyzw
ishl r8.xyzw, r5.xyzw, r8.xyzw
and r8.xyzw, r8.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r5.xyzw, r7.xyzw, r5.xyzw, r8.xyzw
ishl r7.xyzw, r9.xyzw, l(23, 23, 23, 23)
iadd r7.xyzw, r7.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
iadd r5.xyzw, r7.xyzw, r5.xyzw
movc r5.xyzw, r6.xyzw, r5.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r2.yyyy, r5.xyzw
ushr r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
ubfe r3.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r3.xyzw
ushr r6.xyzw, r5.xyzw, l(20, 20, 20, 20)
firstbit_hi r7.xyzw, r3.xyzw
iadd r7.xyzw, r7.xyzw, l(-11, -11, -11, -11)
movc r7.xyzw, r3.xyzw, r7.xyzw, l(21,21,21,21)
iadd r8.xyzw, -r7.xyzw, l(1, 1, 1, 1)
movc r8.xyzw, r6.xyzw, r6.xyzw, r8.xyzw
ishl r7.xyzw, r3.xyzw, r7.xyzw
and r7.xyzw, r7.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r3.xyzw, r6.xyzw, r3.xyzw, r7.xyzw
ishl r6.xyzw, r8.xyzw, l(23, 23, 23, 23)
iadd r6.xyzw, r6.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
iadd r3.xyzw, r6.xyzw, r3.xyzw
movc r3.xyzw, r5.xyzw, r3.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r4.yyyy, r3.xyzw
ld r3.xyzw, r0.yyyy, T0[0].zwxy
if_nz r1.x
  ishl r5.xyzw, r3.zwxy, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r3.zwxy, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r5.zwxy, r6.zwxy
endif 
if_nz r1.y
  ushr r5.xyzw, r3.zwxy, l(16, 16, 16, 16)
  bfi r3.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r5.zwxy
  mov r5.xy, r3.zwzz
else 
  mov r5.xy, r3.zwzz
endif 
ld r0.xyzw, r0.zzzz, T0[0].xyzw
if_nz r1.x
  ishl r6.xyzw, r0.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r7.xyzw, r0.xyzw, l(8, 8, 8, 8)
  and r7.xyzw, r7.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r0.xyzw, r6.xyzw, r7.xyzw
endif 
if_nz r1.y
  ushr r1.xyzw, r0.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r0.xyzw, r1.xyzw
  mov r5.zw, r1.xxxy
  mov r3.zw, r1.zzzw
else 
  mov r5.zw, r0.xxxy
  mov r3.zw, r0.zzzw
endif 
ushr r0.xyzw, r5.xyzw, l(8, 8, 8, 8)
ubfe r1.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r5.xyzw
ushr r5.xyzw, r0.xyzw, l(20, 20, 20, 20)
firstbit_hi r6.xyzw, r1.xyzw
iadd r6.xyzw, r6.xyzw, l(-11, -11, -11, -11)
movc r6.xyzw, r1.xyzw, r6.xyzw, l(21,21,21,21)
iadd r7.xyzw, -r6.xyzw, l(1, 1, 1, 1)
movc r7.xyzw, r5.xyzw, r5.xyzw, r7.xyzw
ishl r6.xyzw, r1.xyzw, r6.xyzw
and r6.xyzw, r6.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r1.xyzw, r5.xyzw, r1.xyzw, r6.xyzw
ishl r5.xyzw, r7.xyzw, l(23, 23, 23, 23)
iadd r5.xyzw, r5.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
iadd r1.xyzw, r5.xyzw, r1.xyzw
movc r0.xyzw, r0.xyzw, r1.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r2.zzzz, r0.xyzw
ushr r0.xyzw, r3.xyzw, l(8, 8, 8, 8)
ubfe r1.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r3.xyzw
ushr r2.xyzw, r0.xyzw, l(20, 20, 20, 20)
firstbit_hi r3.xyzw, r1.xyzw
iadd r3.xyzw, r3.xyzw, l(-11, -11, -11, -11)
movc r3.xyzw, r1.xyzw, r3.xyzw, l(21,21,21,21)
iadd r5.xyzw, -r3.xyzw, l(1, 1, 1, 1)
movc r5.xyzw, r2.xyzw, r2.xyzw, r5.xyzw
ishl r3.xyzw, r1.xyzw, r3.xyzw
and r3.xyzw, r3.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r1.xyzw, r2.xyzw, r1.xyzw, r3.xyzw
ishl r2.xyzw, r5.xyzw, l(23, 23, 23, 23)
iadd r2.xyzw, r2.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
iadd r1.xyzw, r2.xyzw, r1.xyzw
movc r0.xyzw, r0.xyzw, r1.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r4.zzzz, r0.xyzw
ret 
// Approximately 356 instruction slots used
