//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint2 xe_texture_load_guest_storage_width_height;// Offset:    8 Size:     8
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_is_3d_endian; // Offset:   28 Size:     4
//   uint xe_texture_load_host_base;    // Offset:   32 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   36 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   40 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint4         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 8
dcl_thread_group 8, 32, 1
ishl r0.x, vThreadID.x, l(2)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][1].xyzx
or r0.z, r1.y, r1.x
or r0.z, r1.z, r0.z
if_nz r0.z
  ret 
endif 
ishl r0.yz, r0.xxyx, l(0, 2, 2, 0)
ishl r0.y, r0.y, l(1)
imad r0.z, vThreadID.z, CB0[0][2].z, r0.z
imad r0.y, r0.z, CB0[0][2].y, r0.y
iadd r0.y, r0.y, CB0[0][2].x
ushr r0.z, CB0[0][2].y, l(4)
ieq r0.w, CB0[0][0].y, l(-1)
if_nz r0.w
  and r1.x, CB0[0][1].w, l(1)
  if_nz r1.x
    iadd r1.xy, CB0[0][0].wzww, l(31, 31, 0, 0)
    ishr r2.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
    and r1.x, r1.x, l(0x0ffffffe)
    imad r1.x, r2.y, r1.x, r2.x
    ibfe r1.zw, l(0, 0, 27, 29), l(0, 0, 3, 1), vThreadID.xxxx
    imad r1.x, r1.x, r1.y, r1.z
    ishl r1.y, vThreadID.y, l(11)
    and r1.y, r1.y, l(0x00003000)
    bfi r1.y, l(3), l(9), r0.x, r1.y
    ishr r1.y, r1.y, l(6)
    iadd r1.z, r2.y, r2.z
    bfi r2.x, l(1), l(1), r1.z, l(0)
    iadd r1.w, r1.w, r2.x
    bfi r1.w, l(2), l(1), r1.w, l(0)
    bfi r1.z, l(1), l(0), r1.z, r1.w
    bfi r1.xw, l(19, 0, 0, 19), l(11, 0, 0, 14), r1.xxxx, l(0, 0, 0, 0)
    imad r1.xy, r1.yyyy, l(2, 16, 0, 0), r1.xwxx
    bfi r1.xy, l(2, 2, 0, 0), l(9, 12, 0, 0), vThreadID.zzzz, r1.xyxx
    bfi r1.w, l(1), l(4), vThreadID.y, l(0)
    ubfe r2.x, l(3), l(6), r1.x
    and r2.y, r1.z, l(6)
    bfi r1.z, l(1), l(8), r1.z, l(0)
    imad r1.z, r2.x, l(32), r1.z
    imad r1.z, r2.y, l(4), r1.z
    bfi r1.xy, l(6, 6, 0, 0), l(0, 3, 0, 0), r1.wwww, r1.xyxx
    bfi r1.y, l(9), l(3), r1.z, r1.y
    bfi r1.x, l(6), l(0), r1.x, r1.y
  else 
    ibfe r1.yz, l(0, 27, 29, 0), l(0, 3, 1, 0), vThreadID.xxxx
    ishr r2.xy, vThreadID.yyyy, l(5, 2, 0, 0)
    iadd r1.w, CB0[0][0].z, l(31)
    ushr r1.w, r1.w, l(5)
    imad r1.y, r2.x, r1.w, r1.y
    ishl r2.xz, vThreadID.yyyy, l(6, 0, 7, 0)
    and r2.xz, r2.xxzx, l(896, 0, 2048, 0)
    bfi r1.w, l(3), l(4), r0.x, r2.x
    bfi r1.w, l(22), l(10), r1.y, r1.w
    bfi r2.w, l(1), l(4), vThreadID.y, l(0)
    iadd r1.w, r1.w, r2.w
    ishl r3.xy, r2.xxxx, l(3, 2, 0, 0)
    bfi r3.xy, l(3, 3, 0, 0), l(7, 6, 0, 0), r0.xxxx, r3.xyxx
    bfi r3.xy, l(22, 22, 0, 0), l(13, 12, 0, 0), r1.yyyy, r3.xyxx
    imad r2.xw, r2.wwww, l(8, 0, 0, 4), r3.xxxy
    bfi r1.y, l(12), l(0), r2.z, r2.x
    and r2.x, r2.w, l(1792)
    iadd r1.y, r1.y, r2.x
    and r2.x, r2.y, l(2)
    iadd r1.z, r1.z, r2.x
    bfi r1.z, l(2), l(6), r1.z, l(0)
    iadd r1.y, r1.y, r1.z
    bfi r1.x, l(6), l(0), r1.w, r1.y
  endif 
else 
  ishl r0.x, r0.x, l(3)
  iadd r1.y, CB0[0][1].y, l(31)
  and r1.y, r1.y, l(-32)
  imad r1.y, vThreadID.z, r1.y, vThreadID.y
  imad r1.x, r1.y, CB0[0][0].y, r0.x
endif 
iadd r0.x, r1.x, CB0[0][0].x
ushr r0.xy, r0.xyxx, l(4, 4, 0, 0)
ushr r1.x, CB0[0][1].w, l(1)
ld r2.xyzw, r0.xxxx, T0[0].xzyw
ieq r1.xyz, r1.xxxx, l(1, 2, 3, 0)
or r1.xy, r1.yzyy, r1.xyxx
if_nz r1.x
  ishl r3.xyzw, r2.xzyw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r2.xzyw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r3.xzyw, r4.xzyw
endif 
if_nz r1.y
  ushr r3.xyzw, r2.xzyw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r3.xzyw
endif 
ubfe r1.zw, l(0, 0, 8, 8), l(0, 0, 8, 8), r2.xxxy
bfi r3.xy, l(8, 8, 0, 0), l(16, 16, 0, 0), r2.xyxx, l(0, 0, 0, 0)
iadd r1.zw, r1.zzzw, r3.xxxy
ushr r3.xy, r2.xyxx, l(24, 24, 0, 0)
and r2.xy, r2.xyxx, l(0x00ff0000, 0x00ff0000, 0, 0)
iadd r2.xy, r2.xyxx, r3.xyxx
ishl r3.xy, r2.zwzz, l(1, 1, 0, 0)
and r3.xy, r3.xyxx, l(0xaaaaaaaa, 0xaaaaaaaa, 0, 0)
ushr r2.zw, r2.zzzw, l(0, 0, 1, 1)
and r2.zw, r2.zzzw, l(0, 0, 0x55555555, 0x55555555)
iadd r2.zw, r2.zzzw, r3.xxxy
ushr r3.xy, r2.zwzz, l(1, 1, 0, 0)
and r3.xy, r3.xyxx, l(0x55555555, 0x55555555, 0, 0)
xor r2.zw, r2.zzzw, r3.xxxy
not r3.xy, r2.wzww
ushr r4.yzw, r3.yyyy, l(0, 4, 2, 6)
mov r4.x, r3.y
and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
ushr r5.yzw, r2.zzzz, l(0, 4, 2, 6)
mov r5.x, r2.z
and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
imul null, r5.xyzw, r2.xxxx, r5.xyzw
imad r4.xyzw, r4.xyzw, r1.zzzz, r5.xyzw
and r5.xyzw, r4.xyzw, l(2047, 2047, 2047, 2047)
udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
ushr r4.xyzw, r4.xyzw, l(16, 16, 16, 16)
udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
ishl r4.xyzw, r4.xyzw, l(8, 8, 24, 24)
or r4.xy, r4.xyxx, r5.xyxx
ishl r5.xy, r5.zwzz, l(16, 16, 0, 0)
or r4.xy, r4.xyxx, r5.xyxx
or r4.xy, r4.zwzz, r4.xyxx
ushr r3.yzw, r3.xxxx, l(0, 4, 2, 6)
and r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
ushr r5.yzw, r2.wwww, l(0, 4, 2, 6)
mov r5.x, r2.w
and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
imul null, r5.xyzw, r2.yyyy, r5.xyzw
imad r3.xyzw, r3.xyzw, r1.wwww, r5.xyzw
and r5.xyzw, r3.xyzw, l(2047, 2047, 2047, 2047)
udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
ushr r3.xyzw, r3.xyzw, l(16, 16, 16, 16)
udiv r3.xyzw, null, r3.xyzw, l(3, 3, 3, 3)
ishl r3.xyzw, r3.xyzw, l(8, 8, 24, 24)
or r3.xy, r3.xyxx, r5.xyxx
ishl r5.xy, r5.zwzz, l(16, 16, 0, 0)
or r3.xy, r3.xyxx, r5.xyxx
or r4.zw, r3.zzzw, r3.xxxy
store_uav_typed U0[0].xyzw, r0.yyyy, r4.xyzw
imad r3.x, vThreadID.y, l(4), l(1)
ilt r3.x, r3.x, CB0[0][2].z
if_nz r3.x
  iadd r3.y, r0.z, r0.y
  ushr r4.xy, r2.wzww, l(8, 8, 0, 0)
  not r5.xy, r4.xyxx
  ushr r6.yzw, r5.yyyy, l(0, 4, 2, 6)
  mov r6.x, r5.y
  and r6.xyzw, r6.xyzw, l(3, 3, 3, 3)
  ushr r7.yzw, r4.yyyy, l(0, 4, 2, 6)
  mov r7.x, r4.y
  and r7.xyzw, r7.xyzw, l(3, 3, 3, 3)
  imul null, r7.xyzw, r2.xxxx, r7.xyzw
  imad r6.xyzw, r6.xyzw, r1.zzzz, r7.xyzw
  and r7.xyzw, r6.xyzw, l(2047, 2047, 2047, 2047)
  udiv r7.xyzw, null, r7.xyzw, l(3, 3, 3, 3)
  ushr r6.xyzw, r6.xyzw, l(16, 16, 16, 16)
  udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
  ishl r6.xyzw, r6.xyzw, l(8, 8, 24, 24)
  or r3.zw, r6.xxxy, r7.xxxy
  ishl r6.xy, r7.zwzz, l(16, 16, 0, 0)
  or r3.zw, r3.zzzw, r6.xxxy
  or r6.xy, r6.zwzz, r3.zwzz
  ushr r5.yzw, r5.xxxx, l(0, 4, 2, 6)
  and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
  ushr r4.yzw, r4.xxxx, l(0, 4, 2, 6)
  and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
  imul null, r4.xyzw, r2.yyyy, r4.xyzw
  imad r4.xyzw, r5.xyzw, r1.wwww, r4.xyzw
  and r5.xyzw, r4.xyzw, l(2047, 2047, 2047, 2047)
  udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
  ushr r4.xyzw, r4.xyzw, l(16, 16, 16, 16)
  udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
  ishl r4.xyzw, r4.xyzw, l(8, 8, 24, 24)
  or r3.zw, r4.xxxy, r5.xxxy
  ishl r4.xy, r5.zwzz, l(16, 16, 0, 0)
  or r3.zw, r3.zzzw, r4.xxxy
  or r6.zw, r4.zzzw, r3.zzzw
  store_uav_typed U0[0].xyzw, r3.yyyy, r6.xyzw
  imad r3.y, vThreadID.y, l(4), l(2)
  ilt r3.y, r3.y, CB0[0][2].z
  if_nz r3.y
    ishl r3.y, r0.z, l(1)
    iadd r3.y, r0.y, r3.y
    ushr r4.xy, r2.wzww, l(16, 16, 0, 0)
    not r5.xy, r4.xyxx
    ushr r6.yzw, r5.yyyy, l(0, 4, 2, 6)
    mov r6.x, r5.y
    and r6.xyzw, r6.xyzw, l(3, 3, 3, 3)
    ushr r7.yzw, r4.yyyy, l(0, 4, 2, 6)
    mov r7.x, r4.y
    and r7.xyzw, r7.xyzw, l(3, 3, 3, 3)
    imul null, r7.xyzw, r2.xxxx, r7.xyzw
    imad r6.xyzw, r6.xyzw, r1.zzzz, r7.xyzw
    and r7.xyzw, r6.xyzw, l(2047, 2047, 2047, 2047)
    udiv r7.xyzw, null, r7.xyzw, l(3, 3, 3, 3)
    ushr r6.xyzw, r6.xyzw, l(16, 16, 16, 16)
    udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
    ishl r6.xyzw, r6.xyzw, l(8, 8, 24, 24)
    or r3.zw, r6.xxxy, r7.xxxy
    ishl r6.xy, r7.zwzz, l(16, 16, 0, 0)
    or r3.zw, r3.zzzw, r6.xxxy
    or r6.xy, r6.zwzz, r3.zwzz
    ushr r5.yzw, r5.xxxx, l(0, 4, 2, 6)
    and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
    ushr r4.yzw, r4.xxxx, l(0, 4, 2, 6)
    and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
    imul null, r4.xyzw, r2.yyyy, r4.xyzw
    imad r4.xyzw, r5.xyzw, r1.wwww, r4.xyzw
    and r5.xyzw, r4.xyzw, l(2047, 2047, 2047, 2047)
    udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
    ushr r4.xyzw, r4.xyzw, l(16, 16, 16, 16)
    udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
    ishl r4.xyzw, r4.xyzw, l(8, 8, 24, 24)
    or r3.zw, r4.xxxy, r5.xxxy
    ishl r4.xy, r5.zwzz, l(16, 16, 0, 0)
    or r3.zw, r3.zzzw, r4.xxxy
    or r6.zw, r4.zzzw, r3.zzzw
    store_uav_typed U0[0].xyzw, r3.yyyy, r6.xyzw
    imad r3.y, vThreadID.y, l(4), l(3)
    ilt r3.y, r3.y, CB0[0][2].z
    if_nz r3.y
      imad r3.y, l(3), r0.z, r0.y
      ushr r4.xy, r2.wzww, l(24, 24, 0, 0)
      not r5.xy, r4.xyxx
      ushr r6.yzw, r5.yyyy, l(0, 4, 2, 6)
      mov r6.x, r5.y
      and r6.xyzw, r6.xyzw, l(3, 3, 3, 3)
      ushr r7.yzw, r4.yyyy, l(0, 4, 2, 6)
      mov r7.x, r4.y
      and r7.xyzw, r7.xyzw, l(3, 3, 3, 3)
      imul null, r7.xyzw, r2.xxxx, r7.xyzw
      imad r6.xyzw, r6.xyzw, r1.zzzz, r7.xyzw
      and r7.xyzw, r6.xyzw, l(2047, 2047, 2047, 2047)
      udiv r7.xyzw, null, r7.xyzw, l(3, 3, 3, 3)
      ushr r6.xyzw, r6.xyzw, l(16, 16, 16, 16)
      udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
      ishl r6.xyzw, r6.xyzw, l(8, 8, 24, 24)
      or r2.xz, r6.xxyx, r7.xxyx
      ishl r3.zw, r7.zzzw, l(0, 0, 16, 16)
      or r2.xz, r2.xxzx, r3.zzwz
      or r6.xy, r6.zwzz, r2.xzxx
      ushr r5.yzw, r5.xxxx, l(0, 4, 2, 6)
      and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
      ushr r4.yzw, r4.xxxx, l(0, 4, 2, 6)
      and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
      imul null, r2.xyzw, r2.yyyy, r4.xyzw
      imad r2.xyzw, r5.xyzw, r1.wwww, r2.xyzw
      and r4.xyzw, r2.xyzw, l(2047, 2047, 2047, 2047)
      udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
      ushr r2.xyzw, r2.xyzw, l(16, 16, 16, 16)
      udiv r2.xyzw, null, r2.xyzw, l(3, 3, 3, 3)
      ishl r2.xyzw, r2.xyzw, l(8, 8, 24, 24)
      or r1.zw, r2.xxxy, r4.xxxy
      ishl r2.xy, r4.zwzz, l(16, 16, 0, 0)
      or r1.zw, r1.zzzw, r2.xxxy
      or r6.zw, r2.zzzw, r1.zzzw
      store_uav_typed U0[0].xyzw, r3.yyyy, r6.xyzw
    endif 
  endif 
endif 
iadd r0.y, r0.y, l(1)
movc r0.w, r0.w, l(2), l(1)
iadd r0.x, r0.w, r0.x
ld r2.xyzw, r0.xxxx, T0[0].xzyw
if_nz r1.x
  ishl r4.xyzw, r2.xzyw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r5.xyzw, r2.xzyw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r4.xzyw, r5.xzyw
endif 
if_nz r1.y
  ushr r1.xyzw, r2.xzyw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r1.xzyw
endif 
ubfe r0.xw, l(8, 0, 0, 8), l(8, 0, 0, 8), r2.xxxy
bfi r1.xy, l(8, 8, 0, 0), l(16, 16, 0, 0), r2.xyxx, l(0, 0, 0, 0)
iadd r0.xw, r0.xxxw, r1.xxxy
ushr r1.xy, r2.xyxx, l(24, 24, 0, 0)
and r1.zw, r2.xxxy, l(0, 0, 0x00ff0000, 0x00ff0000)
iadd r1.xy, r1.zwzz, r1.xyxx
ishl r1.zw, r2.zzzw, l(0, 0, 1, 1)
and r1.zw, r1.zzzw, l(0, 0, 0xaaaaaaaa, 0xaaaaaaaa)
ushr r2.xy, r2.zwzz, l(1, 1, 0, 0)
and r2.xy, r2.xyxx, l(0x55555555, 0x55555555, 0, 0)
iadd r1.zw, r1.zzzw, r2.xxxy
ushr r2.xy, r1.zwzz, l(1, 1, 0, 0)
and r2.xy, r2.xyxx, l(0x55555555, 0x55555555, 0, 0)
xor r1.zw, r1.zzzw, r2.xxxy
not r2.xy, r1.wzww
ushr r4.yzw, r2.yyyy, l(0, 4, 2, 6)
mov r4.x, r2.y
and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
ushr r5.yzw, r1.zzzz, l(0, 4, 2, 6)
mov r5.x, r1.z
and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
imul null, r5.xyzw, r1.xxxx, r5.xyzw
imad r4.xyzw, r4.xyzw, r0.xxxx, r5.xyzw
and r5.xyzw, r4.xyzw, l(2047, 2047, 2047, 2047)
udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
ushr r4.xyzw, r4.xyzw, l(16, 16, 16, 16)
udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
ishl r4.xyzw, r4.xyzw, l(8, 8, 24, 24)
or r3.yz, r4.xxyx, r5.xxyx
ishl r4.xy, r5.zwzz, l(16, 16, 0, 0)
or r3.yz, r3.yyzy, r4.xxyx
or r4.xy, r4.zwzz, r3.yzyy
ushr r2.yzw, r2.xxxx, l(0, 4, 2, 6)
and r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
ushr r5.yzw, r1.wwww, l(0, 4, 2, 6)
mov r5.x, r1.w
and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
imul null, r5.xyzw, r1.yyyy, r5.xyzw
imad r2.xyzw, r2.xyzw, r0.wwww, r5.xyzw
and r5.xyzw, r2.xyzw, l(2047, 2047, 2047, 2047)
udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
ushr r2.xyzw, r2.xyzw, l(16, 16, 16, 16)
udiv r2.xyzw, null, r2.xyzw, l(3, 3, 3, 3)
ishl r2.xyzw, r2.xyzw, l(8, 8, 24, 24)
or r2.xy, r2.xyxx, r5.xyxx
ishl r3.yz, r5.zzwz, l(0, 16, 16, 0)
or r2.xy, r2.xyxx, r3.yzyy
or r4.zw, r2.zzzw, r2.xxxy
store_uav_typed U0[0].xyzw, r0.yyyy, r4.xyzw
if_nz r3.x
  iadd r2.x, r0.z, r0.y
  ushr r3.xy, r1.wzww, l(8, 8, 0, 0)
  not r4.xy, r3.xyxx
  ushr r5.yzw, r4.yyyy, l(0, 4, 2, 6)
  mov r5.x, r4.y
  and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
  ushr r6.yzw, r3.yyyy, l(0, 4, 2, 6)
  mov r6.x, r3.y
  and r6.xyzw, r6.xyzw, l(3, 3, 3, 3)
  imul null, r6.xyzw, r1.xxxx, r6.xyzw
  imad r5.xyzw, r5.xyzw, r0.xxxx, r6.xyzw
  and r6.xyzw, r5.xyzw, l(2047, 2047, 2047, 2047)
  udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
  ushr r5.xyzw, r5.xyzw, l(16, 16, 16, 16)
  udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
  ishl r5.xyzw, r5.xyzw, l(8, 8, 24, 24)
  or r2.yz, r5.xxyx, r6.xxyx
  ishl r5.xy, r6.zwzz, l(16, 16, 0, 0)
  or r2.yz, r2.yyzy, r5.xxyx
  or r5.xy, r5.zwzz, r2.yzyy
  ushr r4.yzw, r4.xxxx, l(0, 4, 2, 6)
  and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
  ushr r3.yzw, r3.xxxx, l(0, 4, 2, 6)
  and r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
  imul null, r3.xyzw, r1.yyyy, r3.xyzw
  imad r3.xyzw, r4.xyzw, r0.wwww, r3.xyzw
  and r4.xyzw, r3.xyzw, l(2047, 2047, 2047, 2047)
  udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
  ushr r3.xyzw, r3.xyzw, l(16, 16, 16, 16)
  udiv r3.xyzw, null, r3.xyzw, l(3, 3, 3, 3)
  ishl r3.xyzw, r3.xyzw, l(8, 8, 24, 24)
  or r2.yz, r3.xxyx, r4.xxyx
  ishl r3.xy, r4.zwzz, l(16, 16, 0, 0)
  or r2.yz, r2.yyzy, r3.xxyx
  or r5.zw, r3.zzzw, r2.yyyz
  store_uav_typed U0[0].xyzw, r2.xxxx, r5.xyzw
  imad r2.x, vThreadID.y, l(4), l(2)
  ilt r2.x, r2.x, CB0[0][2].z
  if_nz r2.x
    ishl r2.x, r0.z, l(1)
    iadd r2.x, r0.y, r2.x
    ushr r3.xy, r1.wzww, l(16, 16, 0, 0)
    not r4.xy, r3.xyxx
    ushr r5.yzw, r4.yyyy, l(0, 4, 2, 6)
    mov r5.x, r4.y
    and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
    ushr r6.yzw, r3.yyyy, l(0, 4, 2, 6)
    mov r6.x, r3.y
    and r6.xyzw, r6.xyzw, l(3, 3, 3, 3)
    imul null, r6.xyzw, r1.xxxx, r6.xyzw
    imad r5.xyzw, r5.xyzw, r0.xxxx, r6.xyzw
    and r6.xyzw, r5.xyzw, l(2047, 2047, 2047, 2047)
    udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
    ushr r5.xyzw, r5.xyzw, l(16, 16, 16, 16)
    udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
    ishl r5.xyzw, r5.xyzw, l(8, 8, 24, 24)
    or r2.yz, r5.xxyx, r6.xxyx
    ishl r5.xy, r6.zwzz, l(16, 16, 0, 0)
    or r2.yz, r2.yyzy, r5.xxyx
    or r5.xy, r5.zwzz, r2.yzyy
    ushr r4.yzw, r4.xxxx, l(0, 4, 2, 6)
    and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
    ushr r3.yzw, r3.xxxx, l(0, 4, 2, 6)
    and r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
    imul null, r3.xyzw, r1.yyyy, r3.xyzw
    imad r3.xyzw, r4.xyzw, r0.wwww, r3.xyzw
    and r4.xyzw, r3.xyzw, l(2047, 2047, 2047, 2047)
    udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
    ushr r3.xyzw, r3.xyzw, l(16, 16, 16, 16)
    udiv r3.xyzw, null, r3.xyzw, l(3, 3, 3, 3)
    ishl r3.xyzw, r3.xyzw, l(8, 8, 24, 24)
    or r2.yz, r3.xxyx, r4.xxyx
    ishl r3.xy, r4.zwzz, l(16, 16, 0, 0)
    or r2.yz, r2.yyzy, r3.xxyx
    or r5.zw, r3.zzzw, r2.yyyz
    store_uav_typed U0[0].xyzw, r2.xxxx, r5.xyzw
    imad r2.x, vThreadID.y, l(4), l(3)
    ilt r2.x, r2.x, CB0[0][2].z
    if_nz r2.x
      imad r0.y, l(3), r0.z, r0.y
      ushr r2.xy, r1.wzww, l(24, 24, 0, 0)
      not r3.xy, r2.xyxx
      ushr r4.yzw, r3.yyyy, l(0, 4, 2, 6)
      mov r4.x, r3.y
      and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
      ushr r5.yzw, r2.yyyy, l(0, 4, 2, 6)
      mov r5.x, r2.y
      and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
      imul null, r5.xyzw, r1.xxxx, r5.xyzw
      imad r4.xyzw, r4.xyzw, r0.xxxx, r5.xyzw
      and r5.xyzw, r4.xyzw, l(2047, 2047, 2047, 2047)
      udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
      ushr r4.xyzw, r4.xyzw, l(16, 16, 16, 16)
      udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
      ishl r4.xyzw, r4.xyzw, l(8, 8, 24, 24)
      or r0.xz, r4.xxyx, r5.xxyx
      ishl r1.xz, r5.zzwz, l(16, 0, 16, 0)
      or r0.xz, r0.xxzx, r1.xxzx
      or r4.xy, r4.zwzz, r0.xzxx
      ushr r3.yzw, r3.xxxx, l(0, 4, 2, 6)
      and r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
      ushr r2.yzw, r2.xxxx, l(0, 4, 2, 6)
      and r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
      imul null, r1.xyzw, r1.yyyy, r2.xyzw
      imad r1.xyzw, r3.xyzw, r0.wwww, r1.xyzw
      and r2.xyzw, r1.xyzw, l(2047, 2047, 2047, 2047)
      udiv r2.xyzw, null, r2.xyzw, l(3, 3, 3, 3)
      ushr r1.xyzw, r1.xyzw, l(16, 16, 16, 16)
      udiv r1.xyzw, null, r1.xyzw, l(3, 3, 3, 3)
      ishl r1.xyzw, r1.xyzw, l(8, 8, 24, 24)
      or r0.xz, r1.xxyx, r2.xxyx
      ishl r1.xy, r2.zwzz, l(16, 16, 0, 0)
      or r0.xz, r0.xxzx, r1.xxyx
      or r4.zw, r1.zzzw, r0.xxxz
      store_uav_typed U0[0].xyzw, r0.yyyy, r4.xyzw
    endif 
  endif 
endif 
ret 
// Approximately 449 instruction slots used
