xemu/include/hw/riscv at c4b231cbd3198a05bcaaef5c0a6ee3ecebd12e21 - xemu

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Zhenzhong Duan 860bb8b925 hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class

RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed
parent class, class_init on them may corrupt their parent class
fields.

It's lucky that parent_realize and parent_phases are not initialized
or used until now, so just remove the definitions. They can be added
back when really necessary.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250606092406.229833-6-zhenzhong.duan@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

2025-06-10 12:59:09 +02:00

boot_opensbi.h

target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI

2024-10-30 11:22:07 +10:00

boot.h

hw/riscv: Add the checking if DTB overlaps to kernel or initrd

2024-12-20 11:22:47 +10:00

iommu.h

hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class

2025-06-10 12:59:09 +02:00

microchip_pfsoc.h

hw/riscv: Configurable MPFS CLINT timebase freq