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xemu/target
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Richard Henderson 03a0d87e8d target/sh4: Use MO_ALIGN where required 
Mark all memory operations that are not already marked with UNALIGN.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11 09:53:41 +01:00
..
alpha
target/alpha: Use MO_ALIGN where required
2023-05-05 17:05:58 +01:00
arm
target/arm: Add compile time asserts to load/store_cpu_field macros
2023-05-02 15:47:41 +01:00
avr
target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-05 17:05:28 +01:00
cris
target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-05 17:05:28 +01:00
hexagon
target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-05 17:05:28 +01:00
hppa
target/hppa: Use MO_ALIGN for system UNALIGN()
2023-05-05 17:05:58 +01:00
i386
target/i386: Add EPYC-Genoa model to support Zen 4 processor series
2023-05-08 16:35:30 +02:00
loongarch
target/loongarch: Terminate vmstate subsections list
2023-05-10 09:52:36 +01:00
m68k
target/m68k: Fix gen_load_fp for OS_LONG
2023-05-11 09:49:25 +01:00
microblaze
target/microblaze: Remove NB_MMU_MODES define
2023-03-13 06:44:37 -07:00
mips
target/mips: Use MO_ALIGN instead of 0
2023-05-11 09:53:41 +01:00
nios2
target/nios2: Remove TARGET_ALIGNED_ONLY
2023-05-11 09:53:41 +01:00
openrisc
target/openrisc: Remove NB_MMU_MODES define
2023-03-13 06:44:37 -07:00
ppc
tcg: ppc64: Fix mask generation for vextractdm
2023-05-05 12:34:22 -03:00
riscv
target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 10:49:50 +10:00
rx
target/rx: Avoid tcg_const_i32
2023-03-13 06:44:37 -07:00
s390x
target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-05 17:05:28 +01:00
sh4
target/sh4: Use MO_ALIGN where required
2023-05-11 09:53:41 +01:00
sparc
target/sparc: Use cpu_ld*_code_mmu
2023-05-05 17:09:47 +01:00
tricore
target/tricore: Use min/max for saturate
2023-03-13 07:03:39 -07:00
xtensa
target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-05 17:05:29 +01:00
Kconfig
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meson.build
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