xemu/hw/pci-bridge at 845f94de78cb6c063234176ff7c0ac8e430d19fe - xemu

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Jonathan Cameron 845f94de78 hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.

Copied from gen_pcie_root_port.c
Drop the previous code that ensured a valid value in s->width, s->speed
as now a default is provided so this will always be set.

Note this changes the default settings but it is unlikely to have a negative
effect on software as will only affect ports with now downstream device.
All other ports will use the settings from that device.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240916173518.1843023-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

2024-11-04 16:03:24 -05:00

cxl_downstream.c

hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.

2024-11-04 16:03:24 -05:00

cxl_root_port.c

hw/pci-bridge/cxl_root_port: Provide x-speed and x-width properties.

2024-11-04 16:03:24 -05:00

cxl_upstream.c

hw: Use device_class_set_legacy_reset() instead of opencoding

2024-09-13 15:31:44 +01:00

gen_pcie_root_port.c

hw/pci-bridge: Constify VMState