Wilfred Mallawa aecabd50b7 hw: riscv: opentitan: fixup SPI addresses ...

This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.

The address references can be found [1].

[1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-03-03 13:14:50 +10:00

..

boot_opensbi.h

riscv: Add opensbi firmware dynamic support

2020-07-13 17:25:37 -07:00

boot.h

hw/riscv: Remove macros for ELF BIOS image names

2022-01-21 15:52:57 +10:00

microchip_pfsoc.h

hw/riscv: microchip_pfsoc: Use the PLIC config helper function

2021-10-28 14:39:23 +10:00

numa.h

hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

2020-08-25 09:11:35 -07:00

opentitan.h

hw: riscv: opentitan: fixup SPI addresses

2022-03-03 13:14:50 +10:00

riscv_hart.h

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

2020-09-18 14:12:32 -04:00

shakti_c.h

hw/riscv: Connect Shakti UART to Shakti platform

2021-05-11 20:02:06 +10:00

sifive_cpu.h

riscv: Add a sifive_cpu.h to include both E and U cpu type defines

2019-09-17 08:42:46 -07:00

sifive_e.h

sifive_e: Rename memmap enum constants

2020-09-18 13:49:48 -04:00

sifive_u.h

hw/riscv: sifive_u: Use the PLIC config helper function

2021-10-28 14:39:23 +10:00

spike.h

hw/riscv: spike: Allow using binary firmware as bios

2022-01-21 15:52:56 +10:00

virt.h

hw/riscv: virt: Increase maximum number of allowed CPUs

2022-03-03 13:14:50 +10:00