Files
xemu/tests
Peter Maydell 293c76cb48 Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging
target/xtensa: SR reorganization and options for modern cores

Reorganize special register handling to support configurations with
conflicting SR definitions.

Implement options used by the modern xtensa cores:
- memory protection unit;
- block prefetch;
- exclusive access

Add special register definitions and IRQ types for ECC/parity,
gather/scatter and IDMA.

# gpg: Signature made Mon 20 May 2019 18:53:05 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190520-xtensa:
  target/xtensa: implement exclusive access option
  target/xtensa: update list of exception causes
  target/xtensa: implement block prefetch option opcodes
  target/xtensa: implement DIWBUI.P opcode
  target/xtensa: implement MPU option
  target/xtensa: add parity/ECC option SRs
  target/xtensa: define IDMA and gather/scatter IRQ types
  target/xtensa: make internal MMU functions static
  target/xtensa: get rid of centralized SR properties

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-21 10:44:21 +01:00
..
…
2019-02-22 14:07:01 -05:00
2019-03-07 17:28:46 +01:00
2019-03-07 17:28:47 +01:00
2019-03-07 17:28:47 +01:00
2019-03-07 17:28:46 +01:00
2019-03-07 17:28:41 +01:00
2019-03-07 17:28:46 +01:00
2019-03-07 17:28:46 +01:00
2019-03-07 17:28:46 +01:00
2019-05-13 08:58:55 +02:00
2019-03-07 17:28:25 +01:00
2019-03-07 17:28:46 +01:00
2019-03-12 15:18:40 +01:00
2018-08-23 18:46:25 +02:00
2018-12-20 10:29:08 +01:00
2018-12-20 10:29:08 +01:00
2019-03-07 17:28:27 +01:00
2019-03-07 17:28:46 +01:00