Roman Kagan 09cfb2f635 hyperv: address HvSintRoute by X86CPU pointer ...

Use X86CPU pointer to refer to the respective HvSintRoute instead of
vp_index.  This is more convenient and also paves the way for future
enhancements.

Signed-off-by: Roman Kagan <rkagan@virtuozzo.com>
Message-Id: <20180921081836.29230-7-rkagan@virtuozzo.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2018-10-19 13:44:13 +02:00

..

alpha

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

arm

target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write

2018-10-16 17:14:55 +01:00

cris

target/cris/translate: Get rid of qemu_log_separate()

2018-10-16 17:57:23 +02:00

hppa

target/hppa: Raise exception 26 on emulated hardware

2018-10-16 15:32:22 -07:00

i386

hyperv: address HvSintRoute by X86CPU pointer

2018-10-19 13:44:13 +02:00

lm32

Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into staging

2018-06-04 11:28:31 +01:00

m68k

target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn

2018-06-11 12:43:42 +02:00

microblaze

target-microblaze: Rework NOP/zero instruction handling

2018-06-15 09:05:00 +02:00

mips

target/mips: Add definition of nanoMIPS I7200 CPU

2018-08-24 17:51:59 +02:00

moxie

Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into staging

2018-06-04 11:28:31 +01:00

nios2

Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into staging

2018-06-04 11:28:31 +01:00

openrisc

target/openrisc: Fix writes to interrupt mask register

2018-07-03 22:40:33 +09:00

ppc

target/ppc/cpu-models: Re-group the 970 CPUs together again

2018-09-25 11:12:25 +10:00

riscv

riscv: remove define cpu_init()

2018-09-05 09:58:38 -07:00

s390x

s390x/kvm: enable AP instruction interpretation for guest

2018-10-12 11:32:18 +02:00

sh4

sh4: fix use_icount with linux-user

2018-08-20 00:11:06 +02:00

sparc

SPARC64: add icount support

2018-06-17 11:13:06 +01:00

tilegx

Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into staging

2018-06-04 11:28:31 +01:00

tricore

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

unicore32

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

xtensa

target/xtensa: extract gen_check_interrupts call

2018-10-01 11:08:36 -07:00