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Julian Ganz 081aaba705 target/riscv: call plugin trap callbacks 
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.

This change places hooks for RISC-V targets.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Julian Ganz <neither@nut.email>
Message-ID: <20251027110344.2289945-23-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2025-10-29 14:12:43 +00:00
..
insn_trans
target/riscv: Introduce mo_endian() helper
2025-10-24 09:24:08 +10:00
kvm
char: rename CharBackend->CharFrontend
2025-10-28 14:49:52 +01:00
tcg
target/riscv: Fix a uninitialized variable warning
2025-10-24 09:24:08 +10:00
arch_dump.c
…
bitmanip_helper.c
codebase: prepare to remove cpu.h from exec/exec-all.h
2025-04-23 13:52:25 -07:00
common-semi-target.c
include/semihosting/common-semi: extract common_semi API
2025-09-26 09:55:19 +01:00
cpu_bits.h
target: riscv: Add Svrsw60t59b extension support
2025-07-04 21:09:49 +10:00
cpu_cfg_fields.h.inc
target/riscv: Make PMP granularity configurable
2025-10-24 09:24:08 +10:00
cpu_cfg.h
target/riscv: include default value in cpu_cfg_fields.h.inc
2025-05-20 08:18:53 +02:00
cpu_helper.c
target/riscv: call plugin trap callbacks
2025-10-29 14:12:43 +00:00
cpu_user.h
…
cpu_vendorid.h
…
cpu-param.h
tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
2025-04-23 15:07:32 -07:00
cpu-qom.h
target/riscv: Add BOSC's Xiangshan Kunminghu CPU
2025-07-04 21:09:49 +10:00
cpu.c
target/riscv: Make PMP granularity configurable
2025-10-24 09:24:08 +10:00
cpu.h
target/riscv: Make PMP granularity configurable
2025-10-24 09:24:08 +10:00
crypto_helper.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
csr.c
target/riscv: rvv: Replace checking V by checking Zve32x
2025-10-03 13:15:14 +10:00
debug.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
debug.h
…
fpu_helper.c
target/riscv: Fix fcvt.s.bf16 NaN box checking
2025-07-04 21:09:48 +10:00
gdbstub.c
target/riscv: store RISCVCPUDef struct directly in the class
2025-05-20 08:18:53 +02:00
helper.h
target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64
2025-10-03 13:15:14 +10:00
insn16.decode
…
insn32.decode
target/riscv: Fix the rvv reserved encoding of unmasked instructions
2025-05-19 13:39:20 +10:00
instmap.h
…
internals.h
target/riscv: Fix MEPC/SEPC bit masking for IALIGN
2025-07-04 21:09:49 +10:00
Kconfig
…
m128_helper.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
machine.c
target/riscv: rvv: Replace checking V by checking Zve32x
2025-10-03 13:15:14 +10:00
meson.build
include/semihosting/common-semi: extract common_semi API
2025-09-26 09:55:19 +01:00
monitor.c
target/riscv/monitor: Replace legacy cpu_physical_memory_read() call
2025-10-16 17:07:33 +02:00
op_helper.c
target/riscv: Introduce mo_endian_env() helper
2025-10-24 09:24:08 +10:00
pmp.c
target/riscv: Make PMP CSRs conform to WARL constraints
2025-10-24 09:24:08 +10:00
pmp.h
target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0
2025-01-19 09:44:34 +10:00
pmu.c
include/exec: Split out icount.h
2025-04-23 14:08:44 -07:00
pmu.h
…
riscv-qmp-cmds.c
target/riscv/riscv-qmp-cmds.c: coverity-related fixes
2025-10-24 09:24:08 +10:00
sbi_ecall_interface.h
…
th_csr.c
target/riscv: generalize custom CSR functionality
2025-05-20 08:18:53 +02:00
time_helper.c
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
2025-07-04 21:09:48 +10:00
time_helper.h
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
2025-07-04 21:09:48 +10:00
trace-events
target/riscv: add trace in riscv_raise_exception()
2025-01-19 09:44:34 +10:00
trace.h
…
translate.c
target/riscv: Introduce mo_endian() helper
2025-10-24 09:24:08 +10:00
vcrypto_helper.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
vector_helper.c
target/riscv: Replace HOST_BIG_ENDIAN #ifdef with if() check
2025-10-16 17:07:52 +02:00
vector_internals.c
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
2025-03-19 16:39:00 +10:00
vector_internals.h
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
2025-03-19 16:39:00 +10:00
xthead.decode
…
XVentanaCondOps.decode
…
zce_helper.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00