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Merge commit '57999ac9b9d32775efc271e0edfed27b784ee1c6' as 'parallel-rsp'
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Logan McNaughton committed
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#include "../state.hpp"
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#ifdef PARALLEL_INTEGRATION
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#include "../rsp_1.1.h"
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#include "m64p_plugin.h"
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namespace RSP
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{
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extern RSP_INFO rsp;
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extern short MFC0_count[32];
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extern int SP_STATUS_TIMEOUT;
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} // namespace RSP
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#endif
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using namespace RSP;
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extern "C"
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{
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#ifdef INTENSE_DEBUG
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void log_rsp_mem_parallel(void);
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#endif
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int RSP_MFC0(RSP::CPUState *rsp, unsigned rt, unsigned rd)
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{
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rd &= 15;
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uint32_t res = *rsp->cp0.cr[rd];
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if (rt)
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rsp->sr[rt] = res;
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// CFG_MEND_SEMAPHORE_LOCK == 0 by default,
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// so don't bother implementing semaphores.
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// It makes Mario Golf run terribly for some reason.
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#ifdef PARALLEL_INTEGRATION
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// WAIT_FOR_CPU_HOST. From CXD4.
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if (rd == CP0_REGISTER_SP_STATUS)
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{
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RSP::MFC0_count[rt] += 1;
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if (RSP::MFC0_count[rt] >= RSP::SP_STATUS_TIMEOUT)
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{
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*RSP::rsp.SP_STATUS_REG |= SP_STATUS_HALT;
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return MODE_CHECK_FLAGS;
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}
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}
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#endif
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//if (rd == 4) // SP_STATUS_REG
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// fprintf(stderr, "READING STATUS REG!\n");
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return MODE_CONTINUE;
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}
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static inline int rsp_status_write(RSP::CPUState *rsp, uint32_t rt)
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{
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//fprintf(stderr, "Writing 0x%x to status reg!\n", rt);
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uint32_t status = *rsp->cp0.cr[CP0_REGISTER_SP_STATUS];
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if (rt & SP_CLR_HALT)
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status &= ~SP_STATUS_HALT;
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else if (rt & SP_SET_HALT)
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status |= SP_STATUS_HALT;
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if (rt & SP_CLR_BROKE)
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status &= ~SP_STATUS_BROKE;
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if (rt & SP_CLR_INTR)
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*rsp->cp0.irq &= ~1;
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else if (rt & SP_SET_INTR)
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*rsp->cp0.irq |= 1;
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if (rt & SP_CLR_SSTEP)
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status &= ~SP_STATUS_SSTEP;
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else if (rt & SP_SET_SSTEP)
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status |= SP_STATUS_SSTEP;
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if (rt & SP_CLR_INTR_BREAK)
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status &= ~SP_STATUS_INTR_BREAK;
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else if (rt & SP_SET_INTR_BREAK)
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status |= SP_STATUS_INTR_BREAK;
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if (rt & SP_CLR_SIG0)
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status &= ~SP_STATUS_SIG0;
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else if (rt & SP_SET_SIG0)
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status |= SP_STATUS_SIG0;
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if (rt & SP_CLR_SIG1)
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status &= ~SP_STATUS_SIG1;
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else if (rt & SP_SET_SIG1)
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status |= SP_STATUS_SIG1;
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if (rt & SP_CLR_SIG2)
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status &= ~SP_STATUS_SIG2;
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else if (rt & SP_SET_SIG2)
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status |= SP_STATUS_SIG2;
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if (rt & SP_CLR_SIG3)
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status &= ~SP_STATUS_SIG3;
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else if (rt & SP_SET_SIG3)
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status |= SP_STATUS_SIG3;
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if (rt & SP_CLR_SIG4)
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status &= ~SP_STATUS_SIG4;
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else if (rt & SP_SET_SIG4)
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status |= SP_STATUS_SIG4;
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if (rt & SP_CLR_SIG5)
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status &= ~SP_STATUS_SIG5;
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else if (rt & SP_SET_SIG5)
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status |= SP_STATUS_SIG5;
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if (rt & SP_CLR_SIG6)
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status &= ~SP_STATUS_SIG6;
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else if (rt & SP_SET_SIG6)
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status |= SP_STATUS_SIG6;
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if (rt & SP_CLR_SIG7)
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status &= ~SP_STATUS_SIG7;
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else if (rt & SP_SET_SIG7)
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status |= SP_STATUS_SIG7;
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*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] = status;
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return ((*rsp->cp0.irq & 1) || (status & SP_STATUS_HALT)) ? MODE_CHECK_FLAGS : MODE_CONTINUE;
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}
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#ifdef PARALLEL_INTEGRATION
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static int rsp_dma_read(RSP::CPUState *rsp)
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{
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uint32_t length_reg = *rsp->cp0.cr[CP0_REGISTER_DMA_READ_LENGTH];
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uint32_t length = (length_reg & 0xFFF) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFFF;
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unsigned count = (length_reg >> 12) & 0xFF;
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// Force alignment.
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length = (length + 0x7) & ~0x7;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] &= ~0x3;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] &= ~0x7;
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// Check length.
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if (((*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF) + length) > 0x1000)
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length = 0x1000 - (*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF);
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unsigned i = 0;
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uint32_t source = *rsp->cp0.cr[CP0_REGISTER_DMA_DRAM];
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uint32_t dest = *rsp->cp0.cr[CP0_REGISTER_DMA_CACHE];
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#ifdef INTENSE_DEBUG
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fprintf(stderr, "DMA READ: (0x%x <- 0x%x) len %u, count %u, skip %u\n", dest & 0x1ffc, source & 0x7ffffc,
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length, count + 1, skip);
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#endif
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do
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{
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unsigned j = 0;
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do
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{
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uint32_t source_addr = (source + j) & 0x7FFFFC;
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uint32_t dest_addr = (dest + j) & 0x1FFC;
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uint32_t word = rsp->rdram[source_addr >> 2];
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if (dest_addr & 0x1000)
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{
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// Invalidate IMEM.
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unsigned block = (dest_addr & 0xfff) / CODE_BLOCK_SIZE;
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rsp->dirty_blocks |= (0x3 << block) >> 1;
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//rsp->dirty_blocks = ~0u;
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rsp->imem[(dest_addr & 0xfff) >> 2] = word;
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}
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else
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rsp->dmem[dest_addr >> 2] = word;
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j += 4;
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} while (j < length);
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source += length + skip;
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dest += length;
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} while (++i <= count);
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = source;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = dest;
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#ifdef INTENSE_DEBUG
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log_rsp_mem_parallel();
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#endif
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return rsp->dirty_blocks ? MODE_CHECK_FLAGS : MODE_CONTINUE;
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}
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static void rsp_dma_write(RSP::CPUState *rsp)
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{
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uint32_t length_reg = *rsp->cp0.cr[CP0_REGISTER_DMA_WRITE_LENGTH];
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uint32_t length = (length_reg & 0xFFF) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFFF;
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unsigned count = (length_reg >> 12) & 0xFF;
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// Force alignment.
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length = (length + 0x7) & ~0x7;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] &= ~0x3;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] &= ~0x7;
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// Check length.
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if (((*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF) + length) > 0x1000)
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length = 0x1000 - (*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF);
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uint32_t dest = *rsp->cp0.cr[CP0_REGISTER_DMA_DRAM];
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uint32_t source = *rsp->cp0.cr[CP0_REGISTER_DMA_CACHE];
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#ifdef INTENSE_DEBUG
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fprintf(stderr, "DMA WRITE: (0x%x <- 0x%x) len %u, count %u, skip %u\n", dest & 0x7ffffc, source & 0x1ffc,
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length, count + 1, skip);
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#endif
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unsigned i = 0;
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do
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{
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unsigned j = 0;
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do
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{
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uint32_t source_addr = (source + j) & 0x1FFC;
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uint32_t dest_addr = (dest + j) & 0x7FFFFC;
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rsp->rdram[dest_addr >> 2] =
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(source_addr & 0x1000) ? rsp->imem[(source_addr & 0xfff) >> 2] : rsp->dmem[source_addr >> 2];
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j += 4;
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} while (j < length);
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source += length;
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dest += length + skip;
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} while (++i <= count);
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = source;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = dest;
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#ifdef INTENSE_DEBUG
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log_rsp_mem_parallel();
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#endif
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}
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#endif
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int RSP_MTC0(RSP::CPUState *rsp, unsigned rd, unsigned rt)
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{
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uint32_t val = rsp->sr[rt];
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switch (static_cast<CP0Registers>(rd & 15))
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{
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case CP0_REGISTER_DMA_CACHE:
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = val & 0x1fff;
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break;
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case CP0_REGISTER_DMA_DRAM:
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = val & 0xffffff;
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break;
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case CP0_REGISTER_DMA_READ_LENGTH:
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*rsp->cp0.cr[CP0_REGISTER_DMA_READ_LENGTH] = val;
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#ifdef PARALLEL_INTEGRATION
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return rsp_dma_read(rsp);
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#else
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return MODE_DMA_READ;
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#endif
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case CP0_REGISTER_DMA_WRITE_LENGTH:
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*rsp->cp0.cr[CP0_REGISTER_DMA_WRITE_LENGTH] = val;
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#ifdef PARALLEL_INTEGRATION
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rsp_dma_write(rsp);
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#endif
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break;
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case CP0_REGISTER_SP_STATUS:
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return rsp_status_write(rsp, val);
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case CP0_REGISTER_SP_RESERVED:
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// CXD4 forces this to 0.
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*rsp->cp0.cr[CP0_REGISTER_SP_RESERVED] = 0;
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break;
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case CP0_REGISTER_CMD_START:
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#ifdef INTENSE_DEBUG
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fprintf(stderr, "CMD_START 0x%x\n", val & 0xfffffff8u);
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#endif
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*rsp->cp0.cr[CP0_REGISTER_CMD_START] = *rsp->cp0.cr[CP0_REGISTER_CMD_CURRENT] =
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*rsp->cp0.cr[CP0_REGISTER_CMD_END] = val & 0xfffffff8u;
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break;
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case CP0_REGISTER_CMD_END:
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#ifdef INTENSE_DEBUG
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fprintf(stderr, "CMD_END 0x%x\n", val & 0xfffffff8u);
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#endif
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*rsp->cp0.cr[CP0_REGISTER_CMD_END] = val & 0xfffffff8u;
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#ifdef PARALLEL_INTEGRATION
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RSP::rsp.ProcessRdpList();
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#endif
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break;
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case CP0_REGISTER_CMD_CLOCK:
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*rsp->cp0.cr[CP0_REGISTER_CMD_CLOCK] = val;
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break;
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case CP0_REGISTER_CMD_STATUS:
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] &= ~(!!(val & 0x1) << 0);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] |= (!!(val & 0x2) << 0);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] &= ~(!!(val & 0x4) << 1);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] |= (!!(val & 0x8) << 1);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] &= ~(!!(val & 0x10) << 2);
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*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] |= (!!(val & 0x20) << 2);
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*rsp->cp0.cr[CP0_REGISTER_CMD_TMEM_BUSY] &= !(val & 0x40) * -1;
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*rsp->cp0.cr[CP0_REGISTER_CMD_CLOCK] &= !(val & 0x200) * -1;
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break;
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case CP0_REGISTER_CMD_CURRENT:
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case CP0_REGISTER_CMD_BUSY:
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case CP0_REGISTER_CMD_PIPE_BUSY:
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case CP0_REGISTER_CMD_TMEM_BUSY:
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break;
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default:
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*rsp->cp0.cr[rd & 15] = val;
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break;
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}
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return MODE_CONTINUE;
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}
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}
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