diff --git a/parallel-rsp/parallel.cpp b/parallel-rsp/parallel.cpp
index 13abf8f..69f0388 100644
--- a/parallel-rsp/parallel.cpp
+++ b/parallel-rsp/parallel.cpp
@@ -45,8 +45,6 @@ RSP::JIT::CPU cpu;
 #endif
 uint32_t MFC0_count[32];
 uint32_t SP_STATUS_TIMEOUT;
-uint32_t dma0_timer;
-uint32_t dma1_timer;
 } // namespace RSP
 
 extern "C"
@@ -76,20 +74,19 @@ extern "C"
 	}
 #endif
 
-	EXPORT unsigned int CALL DoRspCycles(unsigned int cycles)
+	EXPORT unsigned int CALL DoRspCycles(unsigned int first_run)
 	{
 		if (*RSP::rsp.SP_STATUS_REG & (SP_STATUS_HALT | SP_STATUS_BROKE))
 			return 0;
 
 		// We don't know if Mupen from the outside invalidated our IMEM.
-		RSP::cpu.invalidate_imem();
+		if (first_run)
+			RSP::cpu.invalidate_imem();
 
 		// Run CPU until we either break or we need to fire an IRQ.
 		RSP::cpu.get_state().pc = *RSP::rsp.SP_PC_REG & 0xfff;
 		RSP::cpu.get_state().instruction_count = 0;
 		RSP::cpu.get_state().last_instruction_type = RSP::VU_INSTRUCTION;
-		RSP::dma0_timer = 0;
-		RSP::dma1_timer = 0;
 
 #ifdef INTENSE_DEBUG
 		fprintf(stderr, "RUN TASK: %u\n", RSP::cpu.get_state().pc);
@@ -119,8 +116,6 @@ extern "C"
 		else if (*RSP::rsp.SP_SEMAPHORE_REG != 0) // Semaphore lock fixes.
 		{
 		}
-		else
-			RSP::SP_STATUS_TIMEOUT = 16; // From now on, wait 16 times, not 0x7fff
 
 		// CPU restarts with the correct SIGs.
 		*RSP::rsp.SP_STATUS_REG &= ~SP_STATUS_HALT;
@@ -188,7 +183,7 @@ extern "C"
 		RSP::cpu.get_state().cp0.irq = RSP::rsp.MI_INTR_REG;
 
 		// From CXD4.
-		RSP::SP_STATUS_TIMEOUT = 0xffff;
+		RSP::SP_STATUS_TIMEOUT = 256;
 
 		RSP::cpu.set_dmem(reinterpret_cast<uint32_t *>(Rsp_Info.DMEM));
 		RSP::cpu.set_imem(reinterpret_cast<uint32_t *>(Rsp_Info.IMEM));
diff --git a/parallel-rsp/rsp/cp0.cpp b/parallel-rsp/rsp/cp0.cpp
index ad6f784..4df1f13 100644
--- a/parallel-rsp/rsp/cp0.cpp
+++ b/parallel-rsp/rsp/cp0.cpp
@@ -8,8 +8,6 @@ namespace RSP
 extern RSP_INFO rsp;
 extern uint32_t MFC0_count[32];
 extern uint32_t SP_STATUS_TIMEOUT;
-extern uint32_t dma0_timer;
-extern uint32_t dma1_timer;
 } // namespace RSP
 #endif
 
@@ -24,22 +22,6 @@ extern "C"
 
 	int RSP_MFC0(RSP::CPUState *rsp, unsigned rt, unsigned rd)
 	{
-		if (RSP::dma0_timer && RSP::dma0_timer < rsp->instruction_count) // DMA complete
-		{
-			if (RSP::dma1_timer) // Pending DMA
-			{
-				RSP::dma0_timer = rsp->instruction_count + RSP::dma1_timer;
-				RSP::dma1_timer = 0;
-				*rsp->cp0.cr[CP0_REGISTER_DMA_FULL] = 0;
-				*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] &= ~SP_STATUS_DMA_FULL;
-			}
-			else
-			{
-				RSP::dma0_timer = 0;
-				*rsp->cp0.cr[CP0_REGISTER_DMA_BUSY] = 0;
-				*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] &= ~SP_STATUS_DMA_BUSY;
-			}
-		}
 		rd &= 15;
 		uint32_t res = *rsp->cp0.cr[rd];
 		if (rt)
@@ -55,7 +37,8 @@ extern "C"
 		{
 			--rsp->instruction_count; // Some games check the STATUS reg more than normal since we don't really yield properly
 			RSP::MFC0_count[rt] += 1;
-			if (RSP::MFC0_count[rt] >= RSP::SP_STATUS_TIMEOUT)
+			//We don't return control to the CPU if the RDP FREEZE bit is set, doing so seems to cause flickering
+			if (RSP::MFC0_count[rt] >= RSP::SP_STATUS_TIMEOUT && (*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] & 0x2) == 0)
 			{
 				*RSP::rsp.SP_STATUS_REG |= SP_STATUS_HALT;
 				return MODE_CHECK_FLAGS;
@@ -201,18 +184,6 @@ extern "C"
 #ifdef INTENSE_DEBUG
 		log_rsp_mem_parallel();
 #endif
-		if (*rsp->cp0.cr[CP0_REGISTER_DMA_BUSY] == 0)
-		{
-			*rsp->cp0.cr[CP0_REGISTER_DMA_BUSY] = 1;
-			*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] |= SP_STATUS_DMA_BUSY;
-			RSP::dma0_timer = rsp->instruction_count + (((length * count) / 4) / 1.5); // see https://hcs64.com/dma.html, divided by 1.5 to convert CPU cycles to RCP cycles
-		}
-		else
-		{
-			*rsp->cp0.cr[CP0_REGISTER_DMA_FULL] = 1;
-			*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] |= SP_STATUS_DMA_FULL;
-			RSP::dma1_timer = ((length * count) / 4) / 1.5;
-		}
 		return rsp->dirty_blocks ? MODE_CHECK_FLAGS : MODE_CONTINUE;
 	}
 
@@ -265,18 +236,6 @@ extern "C"
 #ifdef INTENSE_DEBUG
 		log_rsp_mem_parallel();
 #endif
-		if (*rsp->cp0.cr[CP0_REGISTER_DMA_BUSY] == 0)
-		{
-			*rsp->cp0.cr[CP0_REGISTER_DMA_BUSY] = 1;
-			*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] |= SP_STATUS_DMA_BUSY;
-			RSP::dma0_timer = rsp->instruction_count + (((length * count) / 4) / 1.5); // see https://hcs64.com/dma.html, divided by 1.5 to convert CPU cycles to RCP cycles
-		}
-		else
-		{
-			*rsp->cp0.cr[CP0_REGISTER_DMA_FULL] = 1;
-			*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] |= SP_STATUS_DMA_FULL;
-			RSP::dma1_timer = ((length * count) / 4) / 1.5;
-		}
 	}
 #endif