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update parallel rsp
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Logan McNaughton committed
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@@ -27,23 +27,22 @@ extern "C"
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if (rt)
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rsp->sr[rt] = res;
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// CFG_MEND_SEMAPHORE_LOCK == 0 by default,
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// so don't bother implementing semaphores.
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// It makes Mario Golf run terribly for some reason.
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#ifdef PARALLEL_INTEGRATION
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// WAIT_FOR_CPU_HOST. From CXD4.
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if (rd == CP0_REGISTER_SP_STATUS)
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{
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--rsp->instruction_count; // Some games check the STATUS reg more than normal since we don't really yield properly
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RSP::MFC0_count[rt] += 1;
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//We don't return control to the CPU if the RDP FREEZE bit is set, doing so seems to cause flickering
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if (RSP::MFC0_count[rt] >= RSP::SP_STATUS_TIMEOUT && (*rsp->cp0.cr[CP0_REGISTER_CMD_STATUS] & 0x2) == 0)
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{
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*RSP::rsp.SP_STATUS_REG |= SP_STATUS_HALT;
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return MODE_CHECK_FLAGS;
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}
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}
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else if (rd == CP0_REGISTER_SP_RESERVED)
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{
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rsp->instruction_count += 2; // Needed for DK64
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RSP::MFC0_count[rt] += 1;
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*rsp->cp0.cr[CP0_REGISTER_SP_RESERVED] = 1;
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}
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if (RSP::MFC0_count[rt] >= RSP::SP_STATUS_TIMEOUT)
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return MODE_EXIT;
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#endif
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//if (rd == 4) // SP_STATUS_REG
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@@ -98,67 +97,67 @@ extern "C"
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uint32_t status = *rsp->cp0.cr[CP0_REGISTER_SP_STATUS];
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if (rt & SP_CLR_HALT)
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if ((rt & SP_CLR_HALT) && !(rt & SP_SET_HALT))
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status &= ~SP_STATUS_HALT;
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else if (rt & SP_SET_HALT)
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if ((rt & SP_SET_HALT) && !(rt & SP_CLR_HALT))
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status |= SP_STATUS_HALT;
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if (rt & SP_CLR_BROKE)
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status &= ~SP_STATUS_BROKE;
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if (rt & SP_CLR_INTR)
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if ((rt & SP_CLR_INTR) && !(rt & SP_SET_INTR))
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*rsp->cp0.irq &= ~1;
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else if (rt & SP_SET_INTR)
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if ((rt & SP_SET_INTR) && !(rt & SP_CLR_INTR))
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*rsp->cp0.irq |= 1;
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if (rt & SP_CLR_SSTEP)
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if ((rt & SP_CLR_SSTEP) && !(rt & SP_SET_SSTEP))
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status &= ~SP_STATUS_SSTEP;
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else if (rt & SP_SET_SSTEP)
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if ((rt & SP_SET_SSTEP) && !(rt & SP_CLR_SSTEP))
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status |= SP_STATUS_SSTEP;
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if (rt & SP_CLR_INTR_BREAK)
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if ((rt & SP_CLR_INTR_BREAK) && !(rt & SP_SET_INTR_BREAK))
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status &= ~SP_STATUS_INTR_BREAK;
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else if (rt & SP_SET_INTR_BREAK)
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if ((rt & SP_SET_INTR_BREAK) && !(rt & SP_CLR_INTR_BREAK))
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status |= SP_STATUS_INTR_BREAK;
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if (rt & SP_CLR_SIG0)
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if ((rt & SP_CLR_SIG0) && !(rt & SP_SET_SIG0))
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status &= ~SP_STATUS_SIG0;
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else if (rt & SP_SET_SIG0)
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if ((rt & SP_SET_SIG0) && !(rt & SP_CLR_SIG0))
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status |= SP_STATUS_SIG0;
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if (rt & SP_CLR_SIG1)
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if ((rt & SP_CLR_SIG1) && !(rt & SP_SET_SIG1))
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status &= ~SP_STATUS_SIG1;
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else if (rt & SP_SET_SIG1)
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if ((rt & SP_SET_SIG1) && !(rt & SP_CLR_SIG1))
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status |= SP_STATUS_SIG1;
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if (rt & SP_CLR_SIG2)
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if ((rt & SP_CLR_SIG2) && !(rt & SP_SET_SIG2))
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status &= ~SP_STATUS_SIG2;
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else if (rt & SP_SET_SIG2)
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if ((rt & SP_SET_SIG2) && !(rt & SP_CLR_SIG2))
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status |= SP_STATUS_SIG2;
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if (rt & SP_CLR_SIG3)
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if ((rt & SP_CLR_SIG3) && !(rt & SP_SET_SIG3))
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status &= ~SP_STATUS_SIG3;
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else if (rt & SP_SET_SIG3)
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if ((rt & SP_SET_SIG3) && !(rt & SP_CLR_SIG3))
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status |= SP_STATUS_SIG3;
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if (rt & SP_CLR_SIG4)
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if ((rt & SP_CLR_SIG4) && !(rt & SP_SET_SIG4))
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status &= ~SP_STATUS_SIG4;
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else if (rt & SP_SET_SIG4)
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if ((rt & SP_SET_SIG4) && !(rt & SP_CLR_SIG4))
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status |= SP_STATUS_SIG4;
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if (rt & SP_CLR_SIG5)
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if ((rt & SP_CLR_SIG5) && !(rt & SP_SET_SIG5))
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status &= ~SP_STATUS_SIG5;
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else if (rt & SP_SET_SIG5)
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if ((rt & SP_SET_SIG5) && !(rt & SP_CLR_SIG5))
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status |= SP_STATUS_SIG5;
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if (rt & SP_CLR_SIG6)
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if ((rt & SP_CLR_SIG6) && !(rt & SP_SET_SIG6))
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status &= ~SP_STATUS_SIG6;
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else if (rt & SP_SET_SIG6)
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if ((rt & SP_SET_SIG6) && !(rt & SP_CLR_SIG6))
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status |= SP_STATUS_SIG6;
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if (rt & SP_CLR_SIG7)
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if ((rt & SP_CLR_SIG7) && !(rt & SP_SET_SIG7))
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status &= ~SP_STATUS_SIG7;
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else if (rt & SP_SET_SIG7)
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if ((rt & SP_SET_SIG7) && !(rt & SP_CLR_SIG7))
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status |= SP_STATUS_SIG7;
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*rsp->cp0.cr[CP0_REGISTER_SP_STATUS] = status;
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@@ -169,14 +168,9 @@ extern "C"
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static int rsp_dma_read(RSP::CPUState *rsp)
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{
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uint32_t length_reg = *rsp->cp0.cr[CP0_REGISTER_DMA_READ_LENGTH];
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uint32_t length = (length_reg & 0xFFF) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFFF;
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unsigned count = (length_reg >> 12) & 0xFF;
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// Force alignment.
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length = (length + 0x7) & ~0x7;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] &= ~0x3;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] &= ~0x7;
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uint32_t length = ((length_reg & 0xFFF) | 7) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFF8;
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unsigned count = ((length_reg >> 12) & 0xFF) + 1;
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// Check length.
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if (((*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF) + length) > 0x1000)
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@@ -216,7 +210,7 @@ extern "C"
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source += length + skip;
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dest += length;
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} while (++i <= count);
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} while (++i < count);
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = source;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = dest;
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@@ -230,14 +224,9 @@ extern "C"
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static void rsp_dma_write(RSP::CPUState *rsp)
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{
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uint32_t length_reg = *rsp->cp0.cr[CP0_REGISTER_DMA_WRITE_LENGTH];
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uint32_t length = (length_reg & 0xFFF) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFFF;
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unsigned count = (length_reg >> 12) & 0xFF;
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// Force alignment.
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length = (length + 0x7) & ~0x7;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] &= ~0x3;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] &= ~0x7;
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uint32_t length = ((length_reg & 0xFFF) | 7) + 1;
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uint32_t skip = (length_reg >> 20) & 0xFF8;
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unsigned count = ((length_reg >> 12) & 0xFF) + 1;
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// Check length.
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if (((*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] & 0xFFF) + length) > 0x1000)
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@@ -269,7 +258,7 @@ extern "C"
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source += length;
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dest += length + skip;
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} while (++i <= count);
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} while (++i < count);
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = source;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = dest;
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@@ -286,11 +275,11 @@ extern "C"
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switch (static_cast<CP0Registers>(rd & 15))
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{
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case CP0_REGISTER_DMA_CACHE:
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = val & 0x1fff;
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*rsp->cp0.cr[CP0_REGISTER_DMA_CACHE] = val & 0x1ff8;
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break;
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case CP0_REGISTER_DMA_DRAM:
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = val & 0xffffff;
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*rsp->cp0.cr[CP0_REGISTER_DMA_DRAM] = val & 0xfffff8;
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break;
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case CP0_REGISTER_DMA_READ_LENGTH:
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@@ -312,7 +301,6 @@ extern "C"
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return rsp_status_write(rsp, val);
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case CP0_REGISTER_SP_RESERVED:
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// CXD4 forces this to 0.
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*rsp->cp0.cr[CP0_REGISTER_SP_RESERVED] = 0;
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break;
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