mirror of
https://github.com/simple64/simple64.git
synced 2026-11-05 23:23:32 +01:00
update parallel rdp
This commit is contained in:
Logan McNaughton committed
1 parent
dcbad003a2
commit
7f8cbf14d8
1 file changed
+87
-97
@@ -21,7 +21,6 @@ static QT_WSIPlatform* wsi_platform;
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int32_t vk_rescaling;
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bool vk_ssreadbacks;
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bool vk_ssdither;
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bool running = false;
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unsigned width, height;
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unsigned vk_overscan;
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unsigned vk_vertical_stretch;
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@@ -238,114 +237,108 @@ static void render_frame(Vulkan::Device &device)
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void vk_rasterize()
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{
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if (processor && running)
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{
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processor->set_vi_register(RDP::VIRegister::Control, *GET_GFX_INFO(VI_STATUS_REG));
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processor->set_vi_register(RDP::VIRegister::Origin, *GET_GFX_INFO(VI_ORIGIN_REG));
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processor->set_vi_register(RDP::VIRegister::Width, *GET_GFX_INFO(VI_WIDTH_REG));
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processor->set_vi_register(RDP::VIRegister::Intr, *GET_GFX_INFO(VI_INTR_REG));
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processor->set_vi_register(RDP::VIRegister::VCurrentLine, *GET_GFX_INFO(VI_V_CURRENT_LINE_REG));
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processor->set_vi_register(RDP::VIRegister::Timing, *GET_GFX_INFO(VI_V_BURST_REG));
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processor->set_vi_register(RDP::VIRegister::VSync, *GET_GFX_INFO(VI_V_SYNC_REG));
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processor->set_vi_register(RDP::VIRegister::HSync, *GET_GFX_INFO(VI_H_SYNC_REG));
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processor->set_vi_register(RDP::VIRegister::Leap, *GET_GFX_INFO(VI_LEAP_REG));
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processor->set_vi_register(RDP::VIRegister::HStart, *GET_GFX_INFO(VI_H_START_REG));
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processor->set_vi_register(RDP::VIRegister::VStart, *GET_GFX_INFO(VI_V_START_REG));
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processor->set_vi_register(RDP::VIRegister::VBurst, *GET_GFX_INFO(VI_V_BURST_REG));
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processor->set_vi_register(RDP::VIRegister::XScale, *GET_GFX_INFO(VI_X_SCALE_REG));
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processor->set_vi_register(RDP::VIRegister::YScale, *GET_GFX_INFO(VI_Y_SCALE_REG));
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processor->set_vi_register(RDP::VIRegister::Control, *GET_GFX_INFO(VI_STATUS_REG));
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processor->set_vi_register(RDP::VIRegister::Origin, *GET_GFX_INFO(VI_ORIGIN_REG));
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processor->set_vi_register(RDP::VIRegister::Width, *GET_GFX_INFO(VI_WIDTH_REG));
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processor->set_vi_register(RDP::VIRegister::Intr, *GET_GFX_INFO(VI_INTR_REG));
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processor->set_vi_register(RDP::VIRegister::VCurrentLine, *GET_GFX_INFO(VI_V_CURRENT_LINE_REG));
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processor->set_vi_register(RDP::VIRegister::Timing, *GET_GFX_INFO(VI_V_BURST_REG));
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processor->set_vi_register(RDP::VIRegister::VSync, *GET_GFX_INFO(VI_V_SYNC_REG));
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processor->set_vi_register(RDP::VIRegister::HSync, *GET_GFX_INFO(VI_H_SYNC_REG));
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processor->set_vi_register(RDP::VIRegister::Leap, *GET_GFX_INFO(VI_LEAP_REG));
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processor->set_vi_register(RDP::VIRegister::HStart, *GET_GFX_INFO(VI_H_START_REG));
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processor->set_vi_register(RDP::VIRegister::VStart, *GET_GFX_INFO(VI_V_START_REG));
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processor->set_vi_register(RDP::VIRegister::VBurst, *GET_GFX_INFO(VI_V_BURST_REG));
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processor->set_vi_register(RDP::VIRegister::XScale, *GET_GFX_INFO(VI_X_SCALE_REG));
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processor->set_vi_register(RDP::VIRegister::YScale, *GET_GFX_INFO(VI_Y_SCALE_REG));
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RDP::Quirks quirks;
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quirks.set_native_texture_lod(vk_native_texture_lod);
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quirks.set_native_resolution_tex_rect(vk_native_tex_rect);
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processor->set_quirks(quirks);
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RDP::Quirks quirks;
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quirks.set_native_texture_lod(vk_native_texture_lod);
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quirks.set_native_resolution_tex_rect(vk_native_tex_rect);
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processor->set_quirks(quirks);
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auto &device = wsi->get_device();
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wsi->begin_frame();
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render_frame(device);
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(*render_callback)(1);
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wsi->end_frame();
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wsi->get_device().promote_read_write_caches_to_read_only();
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}
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auto &device = wsi->get_device();
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wsi->begin_frame();
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render_frame(device);
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(*render_callback)(1);
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wsi->end_frame();
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wsi->get_device().promote_read_write_caches_to_read_only();
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}
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void vk_process_commands()
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{
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if (running)
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const uint32_t DP_CURRENT = *GET_GFX_INFO(DPC_CURRENT_REG) & 0x00FFFFF8;
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const uint32_t DP_END = *GET_GFX_INFO(DPC_END_REG) & 0x00FFFFF8;
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int length = DP_END - DP_CURRENT;
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if (length <= 0)
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return;
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length = unsigned(length) >> 3;
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if ((cmd_ptr + length) & ~(0x0003FFFF >> 3))
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return;
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uint32_t offset = DP_CURRENT;
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if (*GET_GFX_INFO(DPC_STATUS_REG) & DP_STATUS_XBUS_DMA)
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{
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const uint32_t DP_CURRENT = *GET_GFX_INFO(DPC_CURRENT_REG) & 0x00FFFFF8;
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const uint32_t DP_END = *GET_GFX_INFO(DPC_END_REG) & 0x00FFFFF8;
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int length = DP_END - DP_CURRENT;
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if (length <= 0)
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do
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{
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offset &= 0xFF8;
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cmd_data[2 * cmd_ptr + 0] = *reinterpret_cast<const uint32_t *>(SP_DMEM + offset);
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cmd_data[2 * cmd_ptr + 1] = *reinterpret_cast<const uint32_t *>(SP_DMEM + offset + 4);
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offset += sizeof(uint64_t);
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cmd_ptr++;
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} while (--length > 0);
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}
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else
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{
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if (DP_END > 0x7ffffff || DP_CURRENT > 0x7ffffff)
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{
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return;
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length = unsigned(length) >> 3;
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if ((cmd_ptr + length) & ~(0x0003FFFF >> 3))
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return;
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uint32_t offset = DP_CURRENT;
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if (*GET_GFX_INFO(DPC_STATUS_REG) & DP_STATUS_XBUS_DMA)
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}
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else
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{
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do
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{
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offset &= 0xFF8;
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cmd_data[2 * cmd_ptr + 0] = *reinterpret_cast<const uint32_t *>(SP_DMEM + offset);
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cmd_data[2 * cmd_ptr + 1] = *reinterpret_cast<const uint32_t *>(SP_DMEM + offset + 4);
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offset &= 0xFFFFF8;
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cmd_data[2 * cmd_ptr + 0] = *reinterpret_cast<const uint32_t *>(DRAM + offset);
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cmd_data[2 * cmd_ptr + 1] = *reinterpret_cast<const uint32_t *>(DRAM + offset + 4);
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offset += sizeof(uint64_t);
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cmd_ptr++;
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} while (--length > 0);
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}
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else
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{
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if (DP_END > 0x7ffffff || DP_CURRENT > 0x7ffffff)
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{
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return;
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}
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else
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{
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do
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{
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offset &= 0xFFFFF8;
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cmd_data[2 * cmd_ptr + 0] = *reinterpret_cast<const uint32_t *>(DRAM + offset);
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cmd_data[2 * cmd_ptr + 1] = *reinterpret_cast<const uint32_t *>(DRAM + offset + 4);
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offset += sizeof(uint64_t);
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cmd_ptr++;
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} while (--length > 0);
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}
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}
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while (cmd_cur - cmd_ptr < 0)
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{
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uint32_t w1 = cmd_data[2 * cmd_cur];
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uint32_t command = (w1 >> 24) & 63;
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int cmd_length = cmd_len_lut[command];
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if (cmd_ptr - cmd_cur - cmd_length < 0)
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{
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*GET_GFX_INFO(DPC_START_REG) = *GET_GFX_INFO(DPC_CURRENT_REG) = *GET_GFX_INFO(DPC_END_REG);
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return;
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}
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if (command >= 8 && processor)
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processor->enqueue_command(cmd_length * 2, &cmd_data[2 * cmd_cur]);
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if (RDP::Op(command) == RDP::Op::SyncFull)
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{
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// For synchronous RDP:
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if (vk_synchronous && processor)
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processor->wait_for_timeline(processor->signal_timeline());
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*gfx.MI_INTR_REG |= DP_INTERRUPT;
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gfx.CheckInterrupts();
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}
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cmd_cur += cmd_length;
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}
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cmd_ptr = 0;
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cmd_cur = 0;
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*GET_GFX_INFO(DPC_START_REG) = *GET_GFX_INFO(DPC_CURRENT_REG) = *GET_GFX_INFO(DPC_END_REG);
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}
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while (cmd_cur - cmd_ptr < 0)
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{
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uint32_t w1 = cmd_data[2 * cmd_cur];
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uint32_t command = (w1 >> 24) & 63;
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int cmd_length = cmd_len_lut[command];
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if (cmd_ptr - cmd_cur - cmd_length < 0)
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{
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*GET_GFX_INFO(DPC_START_REG) = *GET_GFX_INFO(DPC_CURRENT_REG) = *GET_GFX_INFO(DPC_END_REG);
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return;
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}
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if (command >= 8 && processor)
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processor->enqueue_command(cmd_length * 2, &cmd_data[2 * cmd_cur]);
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if (RDP::Op(command) == RDP::Op::SyncFull)
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{
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// For synchronous RDP:
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if (vk_synchronous && processor)
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processor->wait_for_timeline(processor->signal_timeline());
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*gfx.MI_INTR_REG |= DP_INTERRUPT;
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gfx.CheckInterrupts();
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}
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cmd_cur += cmd_length;
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}
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cmd_ptr = 0;
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cmd_cur = 0;
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*GET_GFX_INFO(DPC_START_REG) = *GET_GFX_INFO(DPC_CURRENT_REG) = *GET_GFX_INFO(DPC_END_REG);
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}
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void vk_resize()
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@@ -357,7 +350,6 @@ void vk_resize()
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void vk_destroy()
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{
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screen_close();
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running = false;
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if (processor)
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{
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delete processor;
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@@ -377,7 +369,6 @@ void vk_destroy()
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bool vk_init()
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{
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running = false;
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screen_init();
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screen_set_mode();
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wsi = new WSI;
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@@ -425,7 +416,7 @@ bool vk_init()
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default:
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break;
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}
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if (vk_rescaling >1 && vk_ssreadbacks)
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if (vk_rescaling > 1 && vk_ssreadbacks)
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flags |= RDP::COMMAND_PROCESSOR_FLAG_SUPER_SAMPLED_READ_BACK_BIT;
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if (vk_ssdither)
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flags |= RDP::COMMAND_PROCESSOR_FLAG_SUPER_SAMPLED_DITHER_BIT;
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@@ -446,6 +437,5 @@ bool vk_init()
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if (window_fullscreen)
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screen_toggle_fullscreen();
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running = true;
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return true;
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}
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