diff --git a/parallel-rsp/parallel.cpp b/parallel-rsp/parallel.cpp
index 1ca7a5b..e952c9d 100644
--- a/parallel-rsp/parallel.cpp
+++ b/parallel-rsp/parallel.cpp
@@ -78,6 +78,7 @@ extern "C"
 		if (first_run)
 		{
 			RSP::cpu.get_state().last_instruction_type = RSP::VU_INSTRUCTION;
+			RSP::cpu.get_state().instruction_pipeline = 0;
 			RSP::cpu.invalidate_imem();
 		}
 
diff --git a/parallel-rsp/rsp_jit.cpp b/parallel-rsp/rsp_jit.cpp
index 221f5ac..951e8e3 100644
--- a/parallel-rsp/rsp_jit.cpp
+++ b/parallel-rsp/rsp_jit.cpp
@@ -321,9 +321,21 @@ extern "C"
 	static void add_instruction_count(CPUState *rsp, uint32_t instruction_type)
 	{
 		if (instruction_type == rsp->last_instruction_type)
+		{
 			++rsp->instruction_count;
+			rsp->instruction_pipeline = 0;
+		}
 		else
+		{
 			rsp->last_instruction_type = instruction_type;
+			if (rsp->instruction_pipeline)
+			{
+				++rsp->instruction_count;
+				rsp->instruction_pipeline = 0;
+			}
+			else
+				rsp->instruction_pipeline = 1;
+		}
 	}
 }
 
diff --git a/parallel-rsp/state.hpp b/parallel-rsp/state.hpp
index 9e4ea88..2169819 100644
--- a/parallel-rsp/state.hpp
+++ b/parallel-rsp/state.hpp
@@ -144,6 +144,7 @@ struct CPUState
 	uint32_t pc = 0;
 	uint32_t instruction_count = 0;
 	uint32_t last_instruction_type = 0;
+	uint32_t instruction_pipeline = 0;
 	uint32_t did_mfc0 = 0;
 	uint32_t dirty_blocks = 0;
 	static_assert(CODE_BLOCKS <= 32, "Code blocks must fit in 32-bit register.");