mirror of
https://github.com/shadps4-emu/shadPS4.git
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TheTurtle
9cab1ecba4
GCN has the concept of hardware and software stages. Software stages are the shader stages exposed in graphics APIs like opengl/vulkan, and each software stage runs on a hardware stage. Depending on how many and what software stages are used in a graphics pipeline, the hardware stage a software one is executed on can change, so the mapping is not fixed. The following table from ACO describes the various combinations for HW-SW stages: https://gitlab.freedesktop.org/mesa/mesa/-/blob/c90ae5f7/src/amd/compiler/README.md#gfx6-8 Certain software stages like the vertex and tess eval shader can run a lot of different hardware stages, which creates problems because runtime info is a tagged union on HW stage. Current main uses struct inheritance to make it work, but that will get clunky when more data is added to other stages. In general there is a lack of separation between what data is required when a HW stage is used and what for SW stage. An example is the tess_emulated_primitive variable. This is used for skipping exports in a software vertex shader when tessellation stages have been inserted after it for Quad/RectList emulation, because it is undefined behavior to not export them from the last geometry stage. Having this data field in the HW vertex info is not semantically correct because HW vertex is always the last geometry stage that runs. So this only works when there isnt any HW geometry shader active, as the HW vertex shader is not normally processed in that case. Another example is shader specialization previously checked the HW vertex stage to specialize the fetch shader. This only works on simple VS+PS pipelines when HW VS runs the SW VS. Fetch shader is part of the SW VS state, its run on first geometry stage not the last, and this issue got exposed because of the new state separation. This commit refactors runtime info to contain two tagged unions, one from SW stage and the other HW stage. This makes it obvious what is the scope of each state. When recompiler does a switch on sw stage, it becomes more apparent it should only access sw state members unless it also checks which hw stage it runs on, which will result in less bugs
335 lines
13 KiB
C++
335 lines
13 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/control_flow_graph.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/ir/basic_block.h"
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#include "shader_recompiler/ir/breadth_first_search.h"
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#include "shader_recompiler/ir/ir_emitter.h"
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#include "shader_recompiler/ir/operand_helper.h"
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#include "shader_recompiler/ir/program.h"
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#include "shader_recompiler/ir/reinterpret.h"
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#include "shader_recompiler/profile.h"
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#include "video_core/amdgpu/resource.h"
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namespace Shader::Optimization {
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namespace {
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using SharpLocation = u32;
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bool IsBufferAtomic(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::BufferAtomicIAdd32:
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case IR::Opcode::BufferAtomicIAdd64:
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case IR::Opcode::BufferAtomicISub32:
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case IR::Opcode::BufferAtomicSMin32:
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case IR::Opcode::BufferAtomicSMin64:
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case IR::Opcode::BufferAtomicUMin32:
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case IR::Opcode::BufferAtomicUMin64:
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case IR::Opcode::BufferAtomicFMin32:
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case IR::Opcode::BufferAtomicSMax32:
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case IR::Opcode::BufferAtomicSMax64:
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case IR::Opcode::BufferAtomicUMax32:
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case IR::Opcode::BufferAtomicUMax64:
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case IR::Opcode::BufferAtomicFMax32:
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case IR::Opcode::BufferAtomicInc32:
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case IR::Opcode::BufferAtomicDec32:
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case IR::Opcode::BufferAtomicAnd32:
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case IR::Opcode::BufferAtomicOr32:
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case IR::Opcode::BufferAtomicXor32:
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case IR::Opcode::BufferAtomicSwap32:
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case IR::Opcode::BufferAtomicCmpSwap32:
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case IR::Opcode::BufferAtomicFCmpSwap32:
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return true;
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default:
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return false;
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}
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}
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bool IsBufferStore(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::StoreBufferU8:
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case IR::Opcode::StoreBufferU16:
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case IR::Opcode::StoreBufferU32:
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case IR::Opcode::StoreBufferU32x2:
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case IR::Opcode::StoreBufferU32x3:
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case IR::Opcode::StoreBufferU32x4:
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case IR::Opcode::StoreBufferU64:
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case IR::Opcode::StoreBufferF32:
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case IR::Opcode::StoreBufferF32x2:
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case IR::Opcode::StoreBufferF32x3:
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case IR::Opcode::StoreBufferF32x4:
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case IR::Opcode::StoreBufferFormatF32:
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return true;
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default:
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return IsBufferAtomic(inst);
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}
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}
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bool IsBufferInstruction(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadBufferU8:
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case IR::Opcode::LoadBufferU16:
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case IR::Opcode::LoadBufferU32:
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case IR::Opcode::LoadBufferU32x2:
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case IR::Opcode::LoadBufferU32x3:
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case IR::Opcode::LoadBufferU32x4:
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case IR::Opcode::LoadBufferU64:
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case IR::Opcode::LoadBufferF32:
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case IR::Opcode::LoadBufferF32x2:
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case IR::Opcode::LoadBufferF32x3:
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case IR::Opcode::LoadBufferF32x4:
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case IR::Opcode::LoadBufferFormatF32:
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case IR::Opcode::ReadConstBuffer:
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return true;
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default:
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return IsBufferStore(inst);
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}
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}
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u32 BufferAddressShift(const IR::Inst& inst, AmdGpu::DataFormat data_format) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadBufferU8:
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case IR::Opcode::StoreBufferU8:
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return 0;
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case IR::Opcode::LoadBufferU16:
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case IR::Opcode::StoreBufferU16:
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return 1;
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case IR::Opcode::LoadBufferU64:
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case IR::Opcode::StoreBufferU64:
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case IR::Opcode::BufferAtomicIAdd64:
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case IR::Opcode::BufferAtomicSMax64:
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case IR::Opcode::BufferAtomicSMin64:
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case IR::Opcode::BufferAtomicUMax64:
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case IR::Opcode::BufferAtomicUMin64:
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return 3;
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case IR::Opcode::LoadBufferFormatF32:
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case IR::Opcode::StoreBufferFormatF32: {
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switch (data_format) {
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case AmdGpu::DataFormat::Format8:
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return 0;
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case AmdGpu::DataFormat::Format8_8:
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case AmdGpu::DataFormat::Format16:
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return 1;
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case AmdGpu::DataFormat::Format8_8_8_8:
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case AmdGpu::DataFormat::Format16_16:
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case AmdGpu::DataFormat::Format10_11_11:
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case AmdGpu::DataFormat::Format2_10_10_10:
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case AmdGpu::DataFormat::Format16_16_16_16:
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case AmdGpu::DataFormat::Format32:
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case AmdGpu::DataFormat::Format32_32:
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case AmdGpu::DataFormat::Format32_32_32:
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case AmdGpu::DataFormat::Format32_32_32_32:
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return 2;
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default:
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return 0;
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}
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break;
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}
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case IR::Opcode::ReadConstBuffer:
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// Provided address is already in dwords
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return 0;
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default:
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return 2;
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}
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}
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class Descriptors {
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public:
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explicit Descriptors(Info& info_)
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: info{info_}, buffer_resources{info_.buffers}, image_resources{info_.images},
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sampler_resources{info_.samplers}, fmask_resources(info_.fmasks) {}
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u32 Add(const BufferResource& desc) {
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const u32 index{Add(buffer_resources, desc, [&desc](const auto& existing) {
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return desc.sharp_fetch == existing.sharp_fetch && desc.post_op == existing.post_op &&
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desc.post_op_dw1_mask == existing.post_op_dw1_mask &&
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desc.buffer_type == existing.buffer_type;
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})};
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auto& buffer = buffer_resources[index];
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buffer.used_types |= desc.used_types;
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buffer.is_written |= desc.is_written;
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buffer.is_formatted |= desc.is_formatted;
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return index;
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}
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u32 Add(const ImageResource& desc) {
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const u32 index{Add(image_resources, desc, [&desc](const auto& existing) {
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return desc.sharp_fetch == existing.sharp_fetch && desc.is_array == existing.is_array &&
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desc.mip_fallback_mode == existing.mip_fallback_mode &&
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desc.constant_mip_index == existing.constant_mip_index &&
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desc.post_op == existing.post_op;
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})};
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auto& image = image_resources[index];
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image.is_atomic |= desc.is_atomic;
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image.is_written |= desc.is_written;
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return index;
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}
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u32 Add(const SamplerResource& desc) {
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const u32 index{Add(sampler_resources, desc, [this, &desc](const auto& existing) {
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return desc.sharp_fetch == existing.sharp_fetch && desc.post_op == existing.post_op &&
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desc.post_op_tsharp_dw3_off == existing.post_op_tsharp_dw3_off;
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})};
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return index;
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}
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u32 Add(const FMaskResource& desc) {
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u32 index = Add(fmask_resources, desc, [&desc](const auto& existing) {
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return desc.sharp_idx == existing.sharp_idx;
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});
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return index;
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}
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private:
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template <typename Descriptors, typename Descriptor, typename Func>
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static u32 Add(Descriptors& descriptors, const Descriptor& desc, Func&& pred) {
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const auto it{std::ranges::find_if(descriptors, pred)};
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if (it != descriptors.end()) {
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return static_cast<u32>(std::distance(descriptors.begin(), it));
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}
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descriptors.push_back(desc);
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return static_cast<u32>(descriptors.size()) - 1;
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}
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const Info& info;
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BufferResourceList& buffer_resources;
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ImageResourceList& image_resources;
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SamplerResourceList& sampler_resources;
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FMaskResourceList& fmask_resources;
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};
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} // Anonymous namespace
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void PatchBufferSharp(IR::Block& block, IR::Inst& inst, Info& info, Descriptors& descriptors,
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const Profile& profile) {
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u32 buffer_binding = descriptors.Add(BufferResource{.used_types = IR::Type::U32,
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.buffer_type = BufferType::Guest,
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.is_written = true,
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.is_formatted = false});
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// Replace handle with binding index in buffer resource list.
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(0, ir.Imm32(buffer_binding));
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}
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IR::U32 CalculateBufferAddress(IR::IREmitter& ir, const IR::Inst& inst, const Info& info,
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const AmdGpu::Buffer& buffer, u32 stride) {
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const auto inst_info = inst.Flags<IR::BufferInstInfo>();
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const u32 inst_offset = inst_info.inst_offset.Value();
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const auto is_inst_typed = inst_info.inst_data_fmt != AmdGpu::DataFormat::FormatInvalid;
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const auto data_format = is_inst_typed
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? AmdGpu::RemapDataFormat(inst_info.inst_data_fmt.Value())
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: buffer.GetDataFmt();
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const u32 shift = BufferAddressShift(inst, data_format);
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const u32 mask = (1 << shift) - 1;
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const IR::U32 soffset = IR::GetBufferSOffsetArg(&inst);
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// If address calculation is of the form "index * const_stride + offset" with
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// offset constant and both const_stride and offset are divisible with the
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// element size, apply shift directly.
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if (inst_info.index_enable && !inst_info.voffset_enable && soffset.IsImmediate() &&
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!buffer.swizzle_enable && !buffer.add_tid_enable && (stride & mask) == 0) {
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const u32 total_offset = soffset.U32() + inst_offset;
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if ((total_offset & mask) == 0) {
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// buffer_offset = index * (const_stride >> shift) + (offset >> shift)
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const IR::U32 index = IR::GetBufferIndexArg(&inst);
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return ir.IAdd(ir.IMul(index, ir.Imm32(stride >> shift)),
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ir.Imm32(total_offset >> shift));
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}
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}
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// index = (inst_idxen ? vgpr_index : 0) + (const_add_tid_enable ?
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// thread_id[5:0] : 0)
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IR::U32 index = ir.Imm32(0U);
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if (inst_info.index_enable) {
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const IR::U32 vgpr_index = IR::GetBufferIndexArg(&inst);
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index = ir.IAdd(index, vgpr_index);
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}
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if (buffer.add_tid_enable) {
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ASSERT_MSG(info.sw_stage == SwStage::Compute,
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"Thread ID buffer addressing is not supported outside of compute.");
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const IR::U32 thread_id{ir.LaneId()};
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index = ir.IAdd(index, thread_id);
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}
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// offset = (inst_offen ? vgpr_offset : 0) + inst_offset
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IR::U32 offset = ir.Imm32(inst_offset);
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offset = ir.IAdd(offset, soffset);
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if (inst_info.voffset_enable) {
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const IR::U32 voffset = IR::GetBufferVOffsetArg(&inst);
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offset = ir.IAdd(offset, voffset);
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}
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const IR::U32 const_stride = ir.Imm32(stride);
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IR::U32 buffer_offset;
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if (buffer.swizzle_enable) {
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const IR::U32 const_index_stride = ir.Imm32(buffer.GetIndexStride());
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const IR::U32 const_element_size = ir.Imm32(buffer.GetElementSize());
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// index_msb = index / const_index_stride
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const IR::U32 index_msb{ir.IDiv(index, const_index_stride)};
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// index_lsb = index % const_index_stride
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const IR::U32 index_lsb{ir.IMod(index, const_index_stride)};
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// offset_msb = offset / const_element_size
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const IR::U32 offset_msb{ir.IDiv(offset, const_element_size)};
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// offset_lsb = offset % const_element_size
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const IR::U32 offset_lsb{ir.IMod(offset, const_element_size)};
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// buffer_offset =
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// (index_msb * const_stride + offset_msb * const_element_size) *
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// const_index_stride
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// + index_lsb * const_element_size + offset_lsb
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const IR::U32 buffer_offset_msb = ir.IMul(
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ir.IAdd(ir.IMul(index_msb, const_stride), ir.IMul(offset_msb, const_element_size)),
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const_index_stride);
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const IR::U32 buffer_offset_lsb =
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ir.IAdd(ir.IMul(index_lsb, const_element_size), offset_lsb);
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buffer_offset = ir.IAdd(buffer_offset_msb, buffer_offset_lsb);
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} else {
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// buffer_offset = index * const_stride + offset
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buffer_offset = ir.IAdd(ir.IMul(index, const_stride), offset);
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}
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if (shift != 0) {
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buffer_offset = ir.ShiftRightLogical(buffer_offset, ir.Imm32(shift));
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}
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return buffer_offset;
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}
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void PatchBufferArgs(IR::Block& block, IR::Inst& inst, Info& info) {
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const auto handle = inst.Arg(0);
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const auto buffer_res = info.buffers[handle.U32()];
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const auto buffer = AmdGpu::Buffer::Null();
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// Address of constant buffer reads can be calculated at IR emission time.
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if (inst.GetOpcode() == IR::Opcode::ReadConstBuffer) {
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return;
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}
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(IR::LoadBufferArgs::Address,
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CalculateBufferAddress(ir, inst, info, buffer, buffer.stride));
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}
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void ResourceTrackingPassStub(IR::Program& program, const Profile& profile) {
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// Iterate resource instructions and patch them after finding the sharp.
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auto& info = program.info;
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// Pass 1: Track resource sharps
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Descriptors descriptors{info};
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for (IR::Block* const block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (IsBufferInstruction(inst)) {
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PatchBufferSharp(*block, inst, info, descriptors, profile);
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}
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}
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}
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// Pass 2: Patch instruction args
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for (IR::Block* const block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (IsBufferInstruction(inst)) {
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PatchBufferArgs(*block, inst, info);
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}
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}
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}
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}
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} // namespace Shader::Optimization
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