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https://github.com/hrydgard/ppsspp.git
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115 lines
2.2 KiB
C++
115 lines
2.2 KiB
C++
#include "../../MemMap.h"
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#include "../MIPSAnalyst.h"
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#include "ArmJit.h"
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#include "ArmRegCache.h"
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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// #define CONDITIONAL_DISABLE Comp_Generic(op); return;
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#define CONDITIONAL_DISABLE ;
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#define DISABLE Comp_Generic(op); return;
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namespace MIPSComp
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{
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void Jit::Comp_VPFX(u32 op)
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{
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CONDITIONAL_DISABLE;
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int data = op & 0xFFFFF;
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int regnum = (op >> 24) & 3;
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switch (regnum) {
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case 0: // S
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js.prefixS = data;
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js.prefixSFlag = ArmJitState::PREFIX_KNOWN_DIRTY;
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break;
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case 1: // T
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js.prefixT = data;
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js.prefixTFlag = ArmJitState::PREFIX_KNOWN_DIRTY;
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break;
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case 2: // D
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js.prefixD = data;
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js.prefixDFlag = ArmJitState::PREFIX_KNOWN_DIRTY;
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break;
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}
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}
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void Jit::Comp_SVQ(u32 op)
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{
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DISABLE;
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int imm = (signed short)(op&0xFFFC);
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int vt = (((op >> 16) & 0x1f)) | ((op&1) << 5);
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int rs = _RS;
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switch (op >> 26)
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{
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case 54: //lv.q
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{
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gpr.MapReg(rs);
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SetR0ToEffectiveAddress(rs, imm);
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u8 vregs[4];
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GetVectorRegs(vregs, V_Quad, vt);
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fpr.MapRegsV(vregs, V_Quad, MAP_DIRTY | MAP_NOINIT);
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fpr.ReleaseSpillLocks();
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// Just copy 4 words the easiest way while not wasting registers.
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for (int i = 0; i < 4; i++)
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VLDR(fpr.V(vregs[i]), R0, i * 4);
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}
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break;
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case 62: //sv.q
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{
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gpr.MapReg(rs);
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SetR0ToEffectiveAddress(rs, imm);
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u8 vregs[4];
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GetVectorRegs(vregs, V_Quad, vt);
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// Even if we don't use real SIMD there's still 8 or 16 scalar float registers.
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fpr.MapRegsV(vregs, V_Quad, 0);
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fpr.ReleaseSpillLocks();
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// Just copy 4 words the easiest way while not wasting registers.
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for (int i = 0; i < 4; i++)
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VSTR(fpr.V(vregs[i]), R0, i * 4);
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}
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break;
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default:
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DISABLE;
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break;
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}
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}
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void Jit::Comp_VDot(u32 op)
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{
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DISABLE;
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}
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void Jit::Comp_VecDo3(u32 op)
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{
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DISABLE;
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}
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void Jit::Comp_Mftv(u32 op)
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{
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DISABLE;
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}
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void Jit::Comp_SV(u32 op) {
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DISABLE;
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}
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void Jit::Comp_Vmtvc(u32 op) {
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DISABLE;
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}
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}
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