Unknown W. Brackets fcc90095f7 riscv: Enable block linking.

2023-08-12 09:37:02 -07:00

..

RiscVAsm.cpp

riscv: Reduce call bloat using temps.

2023-08-08 23:17:32 -07:00

RiscVCompALU.cpp

riscv: Implement ReverseBits in jit.

2023-08-08 23:17:32 -07:00

RiscVCompBranch.cpp

riscv: Enable block linking.

2023-08-12 09:37:02 -07:00

RiscVCompFPU.cpp

riscv: Reduce call bloat using temps.

2023-08-08 23:17:32 -07:00

RiscVCompLoadStore.cpp

irjit: Move more to IRNativeBackend, split.

2023-08-06 00:16:43 -07:00

RiscVCompSystem.cpp

riscv: Reduce call bloat using temps.

2023-08-08 23:17:32 -07:00

RiscVCompVec.cpp

Merge pull request #17875 from unknownbrackets/riscv-jit

2023-08-09 09:30:15 +02:00

RiscVJit.cpp

riscv: Enable block linking.

2023-08-12 09:37:02 -07:00

RiscVJit.h

riscv: Enable block linking.

2023-08-12 09:37:02 -07:00

RiscVRegCache.cpp

Merge pull request #17815 from unknownbrackets/riscv-jit

2023-07-30 14:49:37 -07:00

RiscVRegCache.h

riscv: Spill registers more intelligently.

2023-07-30 14:24:12 -07:00

RiscVRegCacheFPU.cpp

riscv: Make Vec4Shuffle overlap safe.

2023-08-08 23:00:45 -07:00

RiscVRegCacheFPU.h

riscv: Make Vec4Shuffle overlap safe.

2023-08-08 23:00:45 -07:00