mirror of
https://github.com/hrydgard/ppsspp.git
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135 lines
3.0 KiB
C++
135 lines
3.0 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include <algorithm>
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#include "Core/MemMap.h"
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#include "Core/MIPS/x86/X64IRJit.h"
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#include "Core/MIPS/x86/X64IRRegCache.h"
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// This file contains compilation for vector instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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void X64JitBackend::CompIR_VecArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Add:
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case IROp::Vec4Sub:
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case IROp::Vec4Mul:
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case IROp::Vec4Div:
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case IROp::Vec4Scale:
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case IROp::Vec4Neg:
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case IROp::Vec4Abs:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecAssign(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Init:
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case IROp::Vec4Shuffle:
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case IROp::Vec4Blend:
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CompIR_Generic(inst);
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break;
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case IROp::Vec4Mov:
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regs_.Map(inst);
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecClamp(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4ClampToZero:
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case IROp::Vec2ClampToZero:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecHoriz(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Dot:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecPack(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec2Unpack16To31:
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case IROp::Vec4Pack32To8:
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case IROp::Vec2Pack31To16:
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case IROp::Vec4Unpack8To32:
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case IROp::Vec2Unpack16To32:
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case IROp::Vec4DuplicateUpperBitsAndShift1:
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case IROp::Vec4Pack31To8:
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case IROp::Vec2Pack32To16:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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#endif
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