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Henrik RydgårdandClaude Opus 5.5
e52cc38866
Sysreg (0xBC100000) gets the ME's reset bit (0x4C bit 2), the soft interrupt (0x44, which interrupts the other CPU: the ME's controller from the main CPU, PSP_MECODEC_INTR from the ME), the hardware mutex (0x48, each CPU sets its own bit only while the other's is clear) and the clock and config registers it writes. The ME's interrupt controller (0xBC300000, write-1-to-clear, mask at 8) answers the ME only. All of it is the ME's state and stays unhandled without an ME. On the ME: interrupts to EBase with EPC and EXL, halt sleeping until an unmasked interrupt, and Count, which doesn't run: it stays 0 across 10ms with ERL set after reset and with Status cleared, and reads back what was written. Reset keeps the GPRs and sets Status ERL/BEV/SR, which homebrew relies on: mcidclan's samples run C on the stack Sony's ME code left. The values are from a kernel probe on a PSP-1000 (sp 0x801FFFE0, COP0 22 = 1, Status 0x20500404, mfic 0, which doesn't gate interrupts). The main CPU runs base interrupt handlers the way interruptman calls them (a0 intno, a1 arg, a2 interrupted pc; -2 disables), and interrupt 31 has a stand-in for me_wrapper's handler, which homebrew releases first. While the ME is emulated, any main CPU code may access hardware registers: homebrew calls its own code in kernel mode through a kcall module. This is a stopgap (g_kernelModeAnywhere, marked HACK): kernel mode should be part of the CPU's state, switched on while a kernel module's export runs. The memcpy/memmove replacements copy through MMIO when an end is a register address, for code copied to the boot page. mcidclan's me-soft-interrupt sample now runs, counting each interrupt in both directions. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
90 lines
3.1 KiB
C++
90 lines
3.1 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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// The Media Engine, the PSP's second Allegrex. The firmware runs its codecs on it, and homebrew
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// whatever it likes. It runs in its own address space (Memory::CreateMESpace()), on the
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// interpreter, a slice behind the main CPU: CoreTiming runs it for the cycles the main CPU has just
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// used. Only emulated for homebrew, when enabled; commercial games get the HLE codecs.
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#pragma once
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#include "Common/CommonTypes.h"
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#include "Core/MIPS/MIPS.h"
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class PointerWrap;
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namespace MeCore {
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// The ME's interrupt controller's source for the main CPU's soft interrupt (0xBC100044).
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enum : u32 {
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ME_INTR_SOFT = 0x80000000,
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};
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struct MEState {
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MIPSState cpu;
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// Held in reset until the main CPU releases it.
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bool inReset = true;
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// Stopped by halt, until an interrupt it doesn't mask is raised.
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bool halted = false;
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// The ME's clock is tickBase - cpu.downcount.
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s64 tickBase = 0;
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// mfic/mtic's interrupt enable, which is per CPU.
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u32 interruptEnable = 0;
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// Its interrupt controller (0xBC300000): raised sources, and the ones that reach the CPU (IP2).
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u32 intcRaised = 0;
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u32 intcEnabled = 0;
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// System registers (0xBC100000): those the ME code we run uses.
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u32 resetFlags = 0; // 0x4C. Bit 2 holds the ME in reset.
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u32 busClock = 0; // 0x50
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u32 nmiFlags = 0; // 0x04
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u32 ramConfig = 0; // 0x40. Bits 0-1: RAM size, 16 << n MB.
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u32 mutex = 0; // 0x48. Bit 0 is the main CPU's, bit 1 the ME's.
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u32 memProtect[20]{}; // 0xBC000000-0xBC00004C
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};
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// Null when the ME isn't emulated.
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extern MEState *g_meState;
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// Whether the config and this boot (homebrew) want the ME.
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bool Wanted(bool homebrew);
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// Creates the ME, in reset. Fails on platforms without an ME address space.
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bool Init();
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void Shutdown();
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// Creates or removes the ME to match the state.
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void DoState(PointerWrap &p);
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// Runs the ME for the cycles the main CPU has just run.
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void RunFor(int cycles);
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// Asserting reset stops the ME. Releasing it starts the ME at the reset vector.
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void SetReset(bool asserted);
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// The ME's clock.
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u64 GetTicks();
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// COP0 registers with behaviour on the ME: Compare (11), Cause (13).
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u32 ReadCop0(int reg);
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void WriteCop0(int reg, u32 value);
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void Halt();
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// Raises sources in the ME's interrupt controller.
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void RaiseInterrupt(u32 sources);
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// The ME interrupts the main CPU (it wrote 0xBC100044).
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void InterruptMainCPU();
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} // namespace MeCore
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