VACGE/VACGT encoded VMUL, and VACLT didn't swap its operands. The
two-register compares with zero, VCLS, VCLZ and VCNT had the wrong prefix,
VCEQ #0 came out as VEXT, VEXT put its index in the Vm field, VADDHN
encoded VMLAL, and VMLAL/VMLSL lacked bit 23.
VHADD, VHSUB, VMAX and VMIN put the unsigned flag in bit 23, and VQADD,
VMULL and VSHLL dropped it. VQDMULH, VQRDMULH and float VABD ignored Q
registers. VSUB/VABD (IntegerSize) put M in the Q bit. VMOV_neon encoded
0xXX00 in 16-bit lanes as zero. VCVT between F32 and F64 had sz inverted,
and int to F64 took its sign from ROUND_TO_ZERO; double to double now
asserts, since it was never a valid encoding. Lane loads and stores in the
top half of a Q register only worked for 32-bit lanes.
Also fixes asserts that rejected valid D registers (VSUB, VSUBHN, VSWP,
VMLAL/VMLSL) and 64-bit alignment for one and three register VLD1/VST1.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
