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ab809bd19e
Otherwise, the block will be executed with the wrong rounding mode the first time rounding is set. This could be important if it was set for a single operation. This is only a problem the first time it's set.
274 lines
8.2 KiB
C++
274 lines
8.2 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/System.h"
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#include "Core/CoreTiming.h"
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#include "Common/MemoryUtil.h"
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#include "Common/CPUDetect.h"
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#include "Common/ArmEmitter.h"
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#include "Core/MIPS/ARM/ArmJit.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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using namespace ArmGen;
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//static int temp32; // unused?
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static const bool enableDebug = false;
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static const bool disasm = false;
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//static bool enableStatistics = false; //unused?
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//The standard ARM calling convention allocates the 16 ARM registers as:
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// r15 is the program counter.
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// r14 is the link register. (The BL instruction, used in a subroutine call, stores the return address in this register).
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// r13 is the stack pointer. (The Push/Pop instructions in "Thumb" operating mode use this register only).
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// r12 is the Intra-Procedure-call scratch register.
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// r4 to r11: used to hold local variables.
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// r0 to r3: used to hold argument values passed to a subroutine, and also hold results returned from a subroutine.
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// Mappable registers:
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// R2, R3, R4, R5, R6, R8, R11
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// STATIC ALLOCATION ARM:
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// R10 : MIPS state
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// R11 : Memory base pointer.
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// R7 : Down counter
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extern volatile CoreState coreState;
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void ShowPC(u32 sp) {
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ERROR_LOG(JIT, "ShowPC : %08x ArmSP : %08x", currentMIPS->pc, sp);
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// Sleep(1);
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}
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void DisassembleArm(const u8 *data, int size);
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// PLAN: no more block numbers - crazy opcodes just contain offset within
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// dynarec buffer
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// At this offset - 4, there is an int specifying the block number.
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namespace MIPSComp {
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using namespace ArmJitConstants;
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void ArmJit::GenerateFixedCode() {
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const u8 *start = AlignCodePage();
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BeginWrite();
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// LR == SCRATCHREG2 on ARM32 so it needs to be pushed.
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restoreRoundingMode = AlignCode16(); {
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PUSH(1, R_LR);
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VMRS(SCRATCHREG2);
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// Outside the JIT we run with round-to-nearest and flush0 off.
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BIC(SCRATCHREG2, SCRATCHREG2, AssumeMakeOperand2((3 | 4) << 22));
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VMSR(SCRATCHREG2);
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POP(1, R_PC);
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}
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// Must preserve SCRATCHREG1 (R0), destroys SCRATCHREG2 (LR)
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applyRoundingMode = AlignCode16(); {
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PUSH(2, SCRATCHREG1, R_LR);
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LDR(SCRATCHREG2, CTXREG, offsetof(MIPSState, fcr31));
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TST(SCRATCHREG2, AssumeMakeOperand2(1 << 24));
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AND(SCRATCHREG2, SCRATCHREG2, Operand2(3));
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SetCC(CC_NEQ);
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ADD(SCRATCHREG2, SCRATCHREG2, Operand2(4));
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SetCC(CC_AL);
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// We can skip if the rounding mode is nearest (0) and flush is not set.
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// (as restoreRoundingMode cleared it out anyway)
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CMP(SCRATCHREG2, Operand2(0));
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FixupBranch skip = B_CC(CC_EQ);
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// MIPS Rounding Mode: ARM Rounding Mode
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// 0: Round nearest 0
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// 1: Round to zero 3
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// 2: Round up (ceil) 1
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// 3: Round down (floor) 2
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AND(SCRATCHREG1, SCRATCHREG2, Operand2(3));
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CMP(SCRATCHREG1, Operand2(1));
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SetCC(CC_EQ); ADD(SCRATCHREG2, SCRATCHREG2, Operand2(2));
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SetCC(CC_GT); SUB(SCRATCHREG2, SCRATCHREG2, Operand2(1));
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SetCC(CC_AL);
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VMRS(SCRATCHREG1);
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// Assume we're always in round-to-nearest mode beforehand.
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// But we need to clear flush to zero in this case anyway.
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BIC(SCRATCHREG1, SCRATCHREG1, AssumeMakeOperand2((3 | 4) << 22));
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ORR(SCRATCHREG1, SCRATCHREG1, Operand2(SCRATCHREG2, ST_LSL, 22));
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VMSR(SCRATCHREG1);
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SetJumpTarget(skip);
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POP(2, SCRATCHREG1, R_PC);
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}
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FlushLitPool();
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enterDispatcher = AlignCode16();
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DEBUG_LOG(JIT, "Base: %08x", (u32)Memory::base);
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SetCC(CC_AL);
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PUSH(9, R4, R5, R6, R7, R8, R9, R10, R11, R_LR);
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// Take care to 8-byte align stack for function calls.
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// We are misaligned here because of an odd number of args for PUSH.
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// It's not like x86 where you need to account for an extra 4 bytes
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// consumed by CALL.
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SUB(R_SP, R_SP, 4);
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// Now we are correctly aligned and plan to stay that way.
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if (cpu_info.bNEON) {
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VPUSH(D8, 8);
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}
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// Fixed registers, these are always kept when in Jit context.
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// R8 is used to hold flags during delay slots. Not always needed.
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// R13 cannot be used as it's the stack pointer.
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// TODO: Consider statically allocating:
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// * r2-r4
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// Really starting to run low on registers already though...
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// R11, R10, R9
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MOVP2R(MEMBASEREG, Memory::base);
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MOVP2R(CTXREG, mips_);
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MOVP2R(JITBASEREG, GetBasePtr());
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RestoreDowncount();
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MovFromPC(R0);
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outerLoopPCInR0 = GetCodePtr();
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MovToPC(R0);
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outerLoop = GetCodePtr();
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SaveDowncount();
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RestoreRoundingMode(true);
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QuickCallFunction(R0, &CoreTiming::Advance);
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ApplyRoundingMode(true);
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RestoreDowncount();
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FixupBranch skipToCoreStateCheck = B(); //skip the downcount check
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dispatcherCheckCoreState = GetCodePtr();
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// The result of slice decrementation should be in flags if somebody jumped here
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// IMPORTANT - We jump on negative, not carry!!!
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FixupBranch bailCoreState = B_CC(CC_MI);
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SetJumpTarget(skipToCoreStateCheck);
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MOVI2R(R0, (u32)(uintptr_t)&coreState);
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LDR(R0, R0);
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CMP(R0, 0);
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FixupBranch badCoreState = B_CC(CC_NEQ);
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FixupBranch skipToRealDispatch2 = B(); //skip the sync and compare first time
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dispatcherPCInR0 = GetCodePtr();
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// TODO: Do we always need to write PC to RAM here?
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MovToPC(R0);
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// At this point : flags = EQ. Fine for the next check, no need to jump over it.
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dispatcher = GetCodePtr();
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// The result of slice decrementation should be in flags if somebody jumped here
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// IMPORTANT - We jump on negative, not carry!!!
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FixupBranch bail = B_CC(CC_MI);
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SetJumpTarget(skipToRealDispatch2);
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dispatcherNoCheck = GetCodePtr();
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// Debug
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if (enableDebug) {
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MOV(R0, R13);
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QuickCallFunction(R1, (void *)&ShowPC);
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}
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LDR(R0, CTXREG, offsetof(MIPSState, pc));
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// TODO: In practice, do we ever run code from uncached space (| 0x40000000)? If not, we can remove this BIC.
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BIC(R0, R0, Operand2(0xC0, 4)); // &= 0x3FFFFFFF
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LDR(R0, MEMBASEREG, R0);
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AND(R1, R0, Operand2(0xFF, 4)); // rotation is to the right, in 2-bit increments.
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BIC(R0, R0, Operand2(0xFF, 4));
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CMP(R1, Operand2(MIPS_EMUHACK_OPCODE >> 24, 4));
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SetCC(CC_EQ);
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// IDEA - we have 26 bits, why not just use offsets from base of code?
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// Another idea: Shift the bloc number left by two in the op, this would let us do
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// LDR(R0, R9, R0); here, replacing the next instructions.
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#ifdef IOS
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// On iOS, R9 (JITBASEREG) is volatile. We have to reload it.
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MOVI2R(JITBASEREG, (u32)(uintptr_t)GetBasePtr());
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#endif
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ADD(R0, R0, JITBASEREG);
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B(R0);
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SetCC(CC_AL);
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// No block found, let's jit
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SaveDowncount();
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RestoreRoundingMode(true);
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QuickCallFunction(R2, (void *)&MIPSComp::JitAt);
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ApplyRoundingMode(true);
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RestoreDowncount();
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B(dispatcherNoCheck); // no point in special casing this
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SetJumpTarget(bail);
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SetJumpTarget(bailCoreState);
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MOVI2R(R0, (u32)(uintptr_t)&coreState);
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LDR(R0, R0);
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CMP(R0, 0);
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B_CC(CC_EQ, outerLoop);
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SetJumpTarget(badCoreState);
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breakpointBailout = GetCodePtr();
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SaveDowncount();
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RestoreRoundingMode(true);
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// Doing this above the downcount for better pipelining (slightly.)
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if (cpu_info.bNEON) {
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VPOP(D8, 8);
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}
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ADD(R_SP, R_SP, 4);
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POP(9, R4, R5, R6, R7, R8, R9, R10, R11, R_PC); // Returns
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// Uncomment if you want to see the output...
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if (disasm) {
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INFO_LOG(JIT, "THE DISASM ========================");
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DisassembleArm(start, GetCodePtr() - start);
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INFO_LOG(JIT, "END OF THE DISASM ========================");
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}
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// Don't forget to zap the instruction cache!
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FlushLitPool();
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FlushIcache();
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// Let's spare the pre-generated code from unprotect-reprotect.
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AlignCodePage();
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EndWrite();
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}
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} // namespace MIPSComp
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#endif // PPSSPP_ARCH(ARM)
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