Henrik RydgårdandClaude Opus 5.5 985440a0c6 IR regcache: Load a dest that's a later lane of a source ...

When floats are mapped one lane at a time (RISC-V and LoongArch), a NOINIT dest was only upgraded
to a loaded one when a source had the same first reg. In Vec2Pack32To16 vf3, vf2,vf3 the dest is
the source's second lane, so it could be mapped without a load and the op read garbage. Found
with an IR-based ARM32 JIT, which failed vi2s.q C002, C000 in cpu/vfpu/overlap because of it.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-10-14 17:10:35 +02:00

..

IRAnalysis.cpp

IR: Fix PurgeTemps miscompiles

2026-09-24 16:35:11 -06:00

IRAnalysis.h

irjit: Cache IR metadata lookups.

2023-09-30 15:56:53 -07:00

IRCompALU.cpp

Decode the unused bits of shifts and Allegrex bit ops as the PSP does

2026-10-14 10:56:48 +02:00

IRCompBranch.cpp

Drop unused Config.h and SmallDataConvert.h includes

2026-10-13 12:13:42 +02:00

IRCompFPU.cpp

Drop unused Config.h and SmallDataConvert.h includes

2026-10-13 12:13:42 +02:00

IRCompLoadStore.cpp

Drop unused Config.h and SmallDataConvert.h includes

2026-10-13 12:13:42 +02:00

IRCompVFPU.cpp

VFPU: vcmov with imm3 = 7 tests a CC bit that is always clear

2026-10-14 11:59:35 +02:00

IRFrontend.cpp

JITs: Notice a rounding mode that didn't come from a compiled ctc1

2026-10-14 09:26:28 +02:00

IRFrontend.h

JITs: Notice a rounding mode that didn't come from a compiled ctc1

2026-10-14 09:26:28 +02:00

IRInst.cpp

IR interpreter: Merge a conditional exit with the ExitToConst after it

2026-09-25 11:47:17 -06:00

IRInst.h

IR interpreter: Merge a conditional exit with the ExitToConst after it

2026-09-25 11:47:17 -06:00

IRInterpreter.cpp

VFPU: vmin and vmax order zeros and denormals as equal, on every core

2026-10-14 11:59:35 +02:00

IRInterpreter.h

Interpreter: honor the guest's FPU rounding mode and flush-to-zero

2026-08-27 16:43:06 +02:00

IRJit.cpp

JITs: Notice a rounding mode that didn't come from a compiled ctc1

2026-10-14 09:26:28 +02:00

IRJit.h

Keep JIT block entries and replacement hooks out of PSP memory

2026-10-11 10:33:30 +02:00

IRNativeCommon.cpp

JITs: Notice a rounding mode that didn't come from a compiled ctc1

2026-10-14 09:26:28 +02:00

IRNativeCommon.h

Keep JIT block entries and replacement hooks out of PSP memory

2026-10-11 10:33:30 +02:00

IRPassSimplify.cpp

Core: Let 16-bit CPU accesses through the depth mirrors see the GE's layout

2026-10-08 18:37:23 +02:00

IRPassSimplify.h

Add new IR optimization pass, OptimizeLoadsAfterStores

2024-06-07 19:32:37 +02:00

IRRegCache.cpp

IR regcache: Load a dest that's a later lane of a source

2026-10-14 17:10:35 +02:00

IRRegCache.h

IR JIT: Don't store dead temps at exits

2026-09-24 16:38:39 -06:00