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https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
e97ea7bea5
With each lane in its own S register, these are scalar VFP ops per lane, and the packs go through integer registers. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
301 lines
8.0 KiB
C++
301 lines
8.0 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#include "Core/MIPS/ARM/ArmIRJit.h"
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#include "Core/MIPS/ARM/ArmIRRegCache.h"
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// This file contains compilation for Vec4 operations.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace ArmGen;
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using namespace ArmIRJitConstants;
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// Floats aren't mapped as SIMD, so each lane of a Vec4 is its own S register and these work lane
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// by lane. Vec4 regs are aligned to 4, so a dest and a source are either the same or disjoint,
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// but a scalar source can be one of the dest's lanes.
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void ArmJitBackend::CompIR_VecArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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auto lanes3 = [&](void (ARMXEmitter::*op)(ARMReg, ARMReg, ARMReg)) {
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regs_.Map(inst);
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for (int i = 0; i < 4; ++i)
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(this->*op)(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i));
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};
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auto lanes2 = [&](void (ARMXEmitter::*op)(ARMReg, ARMReg)) {
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regs_.Map(inst);
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for (int i = 0; i < 4; ++i)
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(this->*op)(regs_.F(inst.dest + i), regs_.F(inst.src1 + i));
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};
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switch (inst.op) {
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case IROp::Vec4Add:
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lanes3(&ARMXEmitter::VADD);
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break;
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case IROp::Vec4Sub:
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lanes3(&ARMXEmitter::VSUB);
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break;
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case IROp::Vec4Mul:
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lanes3(&ARMXEmitter::VMUL);
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break;
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case IROp::Vec4Div:
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lanes3(&ARMXEmitter::VDIV);
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break;
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case IROp::Vec4Scale:
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regs_.Map(inst);
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// The factor may be one of the dest lanes.
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VMOV(SCRATCHF1, regs_.F(inst.src2));
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for (int i = 0; i < 4; ++i)
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VMUL(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), SCRATCHF1);
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break;
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case IROp::Vec4Neg:
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lanes2(&ARMXEmitter::VNEG);
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break;
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case IROp::Vec4Abs:
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lanes2(&ARMXEmitter::VABS);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_VecAssign(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Init:
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{
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static const float values[7][4] = {
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{ 0.0f, 0.0f, 0.0f, 0.0f },
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{ 1.0f, 1.0f, 1.0f, 1.0f },
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{ -1.0f, -1.0f, -1.0f, -1.0f },
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{ 1.0f, 0.0f, 0.0f, 0.0f },
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{ 0.0f, 1.0f, 0.0f, 0.0f },
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{ 0.0f, 0.0f, 1.0f, 0.0f },
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{ 0.0f, 0.0f, 0.0f, 1.0f },
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};
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if (inst.src1 >= ARRAY_SIZE(values)) {
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CompIR_Generic(inst);
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break;
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}
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regs_.Map(inst);
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for (int i = 0; i < 4; ++i)
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MOVI2F(regs_.F(inst.dest + i), values[inst.src1][i], SCRATCH1);
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break;
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}
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case IROp::Vec4Shuffle:
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regs_.Map(inst);
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if (inst.dest == inst.src1) {
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// Go through the scratch regs, since a lane may be read after it's written.
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for (int i = 0; i < 4; ++i)
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VMOV((ARMReg)(SCRATCHF1 + i), regs_.F(inst.src1 + ((inst.src2 >> (i * 2)) & 3)));
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for (int i = 0; i < 4; ++i)
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VMOV(regs_.F(inst.dest + i), (ARMReg)(SCRATCHF1 + i));
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} else {
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for (int i = 0; i < 4; ++i)
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VMOV(regs_.F(inst.dest + i), regs_.F(inst.src1 + ((inst.src2 >> (i * 2)) & 3)));
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}
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break;
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case IROp::Vec4Blend:
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regs_.Map(inst);
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for (int i = 0; i < 4; ++i) {
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IRReg src = ((inst.constant >> i) & 1) ? inst.src2 : inst.src1;
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if (src != inst.dest)
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VMOV(regs_.F(inst.dest + i), regs_.F(src + i));
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}
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break;
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case IROp::Vec4Mov:
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if (inst.dest != inst.src1) {
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regs_.Map(inst);
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for (int i = 0; i < 4; ++i)
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VMOV(regs_.F(inst.dest + i), regs_.F(inst.src1 + i));
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_VecHoriz(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Dot:
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// In the IR interpreter's order, without fusing, into scratch since dest may be a source lane.
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regs_.Map(inst);
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VMUL(SCRATCHF1, regs_.F(inst.src1), regs_.F(inst.src2));
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for (int i = 1; i < 4; ++i) {
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VMUL(SCRATCHF2, regs_.F(inst.src1 + i), regs_.F(inst.src2 + i));
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VADD(SCRATCHF1, SCRATCHF1, SCRATCHF2);
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}
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VMOV(regs_.F(inst.dest), SCRATCHF1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_VecPack(IRInst inst) {
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CONDITIONAL_DISABLE;
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// These are bit manipulations, so they go through the integer registers. Every source is read
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// before any dest lane is written.
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switch (inst.op) {
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case IROp::Vec2Unpack16To31:
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case IROp::Vec2Unpack16To32:
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{
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regs_.Map(inst);
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VMOV(SCRATCH1, regs_.F(inst.src1));
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bool to31 = inst.op == IROp::Vec2Unpack16To31;
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LSL(SCRATCH2, SCRATCH1, Operand2(16));
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if (to31)
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LSR(SCRATCH2, SCRATCH2, Operand2(1));
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VMOV(regs_.F(inst.dest), SCRATCH2);
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BIC(SCRATCH1, SCRATCH1, Operand2(0xFF, 0));
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BIC(SCRATCH1, SCRATCH1, Operand2(0xFF, 12));
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if (to31)
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LSR(SCRATCH1, SCRATCH1, Operand2(1));
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VMOV(regs_.F(inst.dest + 1), SCRATCH1);
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break;
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}
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case IROp::Vec4Unpack8To32:
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regs_.Map(inst);
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VMOV(SCRATCH1, regs_.F(inst.src1));
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for (int i = 0; i < 4; ++i) {
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// Byte i goes to the top of lane i.
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if (i < 3)
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LSL(SCRATCH2, SCRATCH1, Operand2(24 - i * 8));
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else
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MOV(SCRATCH2, SCRATCH1);
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if (i != 0)
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AND(SCRATCH2, SCRATCH2, Operand2(0xFF, 4));
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VMOV(regs_.F(inst.dest + i), SCRATCH2);
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}
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break;
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case IROp::Vec2Pack32To16:
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regs_.Map(inst);
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VMOV(SCRATCH1, regs_.F(inst.src1));
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VMOV(SCRATCH2, regs_.F(inst.src1 + 1));
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LSR(SCRATCH1, SCRATCH1, Operand2(16));
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// Keep the top half of the second.
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BFI(SCRATCH2, SCRATCH1, 0, 16);
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VMOV(regs_.F(inst.dest), SCRATCH2);
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break;
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case IROp::Vec2Pack31To16:
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// Negative lanes clamp to zero.
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regs_.Map(inst);
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VMOV(SCRATCH1, regs_.F(inst.src1));
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VMOV(SCRATCH2, regs_.F(inst.src1 + 1));
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CMP(SCRATCH1, Operand2(0));
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SetCC(CC_LT);
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MOV(SCRATCH1, Operand2(0));
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SetCC(CC_AL);
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CMP(SCRATCH2, Operand2(0));
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SetCC(CC_LT);
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MOV(SCRATCH2, Operand2(0));
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SetCC(CC_AL);
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LSR(SCRATCH1, SCRATCH1, Operand2(15));
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LSL(SCRATCH2, SCRATCH2, Operand2(1));
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BFI(SCRATCH2, SCRATCH1, 0, 16);
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VMOV(regs_.F(inst.dest), SCRATCH2);
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break;
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case IROp::Vec4Pack32To8:
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case IROp::Vec4Pack31To8:
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{
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// The top byte of each lane (bits 30-23 for 31, with negative lanes as zero.)
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bool from31 = inst.op == IROp::Vec4Pack31To8;
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ARMReg temp = regs_.GetAndLockTempGPR();
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regs_.Map(inst);
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for (int i = 0; i < 4; ++i) {
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ARMReg target = i == 0 ? SCRATCH1 : SCRATCH2;
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VMOV(target, regs_.F(inst.src1 + i));
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if (from31) {
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CMP(target, Operand2(0));
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SetCC(CC_LT);
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MOV(target, Operand2(0));
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SetCC(CC_AL);
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UBFX(target, target, 23, 8);
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} else {
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LSR(target, target, Operand2(24));
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}
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if (i != 0) {
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// Accumulate into temp, then insert at the end.
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if (i == 1)
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MOV(temp, Operand2(target, ST_LSL, 8));
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else
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ORR(temp, temp, Operand2(target, ST_LSL, i * 8));
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}
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}
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ORR(SCRATCH1, SCRATCH1, temp);
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VMOV(regs_.F(inst.dest), SCRATCH1);
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break;
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}
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case IROp::Vec4DuplicateUpperBitsAndShift1:
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regs_.Map(inst);
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for (int i = 0; i < 4; ++i)
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VMOV((ARMReg)(SCRATCHF1 + i), regs_.F(inst.src1 + i));
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for (int i = 0; i < 4; ++i) {
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VMOV(SCRATCH1, (ARMReg)(SCRATCHF1 + i));
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ORR(SCRATCH1, SCRATCH1, Operand2(SCRATCH1, ST_LSR, 8));
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ORR(SCRATCH1, SCRATCH1, Operand2(SCRATCH1, ST_LSR, 16));
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LSR(SCRATCH1, SCRATCH1, Operand2(1));
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VMOV(regs_.F(inst.dest + i), SCRATCH1);
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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#endif
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