mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-07-25 08:14:45 +02:00
605 lines
21 KiB
C++
605 lines
21 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(RISCV64)
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#include "Common/CPUDetect.h"
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#include "Common/Log.h"
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#include "Common/RiscVEmitter.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "GPU/GPUState.h"
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#include "GPU/Common/VertexDecoderCommon.h"
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static const float by128 = 1.0f / 128.0f;
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static const float by16384 = 1.0f / 16384.0f;
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static const float by32768 = 1.0f / 32768.0f;
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static const float const65535 = 65535.0f;
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using namespace RiscVGen;
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static const RiscVReg srcReg = X10;
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static const RiscVReg dstReg = X11;
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static const RiscVReg counterReg = X12;
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static const RiscVReg tempReg1 = X13;
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static const RiscVReg tempReg2 = X14;
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static const RiscVReg tempReg3 = X15;
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static const RiscVReg scratchReg = X16;
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static const RiscVReg fullAlphaReg = X17;
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static const RiscVReg boundsMinUReg = X28;
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static const RiscVReg boundsMinVReg = X29;
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static const RiscVReg boundsMaxUReg = X30;
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static const RiscVReg boundsMaxVReg = X31;
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static const RiscVReg fpScratchReg1 = F10;
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static const RiscVReg fpScratchReg2 = F11;
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static const RiscVReg fpScratchReg3 = F12;
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static const RiscVReg fpSrc[3] = { F13, F14, F15 };
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struct UVScaleRegs {
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struct {
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RiscVReg u;
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RiscVReg v;
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} scale;
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struct {
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RiscVReg u;
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RiscVReg v;
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} offset;
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};
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static const UVScaleRegs prescaleRegs = { { F0, F1 }, { F2, F3 } };
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// TODO: Use vector, where supported.
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static const JitLookup jitLookup[] = {
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{&VertexDecoder::Step_TcU8ToFloat, &VertexDecoderJitCache::Jit_TcU8ToFloat},
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{&VertexDecoder::Step_TcU16ToFloat, &VertexDecoderJitCache::Jit_TcU16ToFloat},
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{&VertexDecoder::Step_TcFloat, &VertexDecoderJitCache::Jit_TcFloat},
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{&VertexDecoder::Step_TcU16ThroughToFloat, &VertexDecoderJitCache::Jit_TcU16ThroughToFloat},
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{&VertexDecoder::Step_TcFloatThrough, &VertexDecoderJitCache::Jit_TcFloatThrough},
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{&VertexDecoder::Step_TcU8Prescale, &VertexDecoderJitCache::Jit_TcU8Prescale},
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{&VertexDecoder::Step_TcU16Prescale, &VertexDecoderJitCache::Jit_TcU16Prescale},
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{&VertexDecoder::Step_TcFloatPrescale, &VertexDecoderJitCache::Jit_TcFloatPrescale},
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{&VertexDecoder::Step_NormalS8, &VertexDecoderJitCache::Jit_NormalS8},
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{&VertexDecoder::Step_NormalS16, &VertexDecoderJitCache::Jit_NormalS16},
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{&VertexDecoder::Step_NormalFloat, &VertexDecoderJitCache::Jit_NormalFloat},
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{&VertexDecoder::Step_PosS8, &VertexDecoderJitCache::Jit_PosS8},
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{&VertexDecoder::Step_PosS16, &VertexDecoderJitCache::Jit_PosS16},
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{&VertexDecoder::Step_PosFloat, &VertexDecoderJitCache::Jit_PosFloat},
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{&VertexDecoder::Step_PosS8Through, &VertexDecoderJitCache::Jit_PosS8Through},
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{&VertexDecoder::Step_PosS16Through, &VertexDecoderJitCache::Jit_PosS16Through},
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{&VertexDecoder::Step_PosFloatThrough, &VertexDecoderJitCache::Jit_PosFloatThrough},
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{&VertexDecoder::Step_Color8888, &VertexDecoderJitCache::Jit_Color8888},
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{&VertexDecoder::Step_Color4444, &VertexDecoderJitCache::Jit_Color4444},
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{&VertexDecoder::Step_Color565, &VertexDecoderJitCache::Jit_Color565},
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{&VertexDecoder::Step_Color5551, &VertexDecoderJitCache::Jit_Color5551},
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};
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JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec, int32_t *jittedSize) {
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dec_ = &dec;
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BeginWrite(4096);
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const u8 *start = AlignCode16();
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SetAutoCompress(true);
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bool log = false;
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bool prescaleStep = false;
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// Look for prescaled texcoord steps
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for (int i = 0; i < dec.numSteps_; i++) {
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if (dec.steps_[i] == &VertexDecoder::Step_TcU8Prescale ||
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dec.steps_[i] == &VertexDecoder::Step_TcU16Prescale ||
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dec.steps_[i] == &VertexDecoder::Step_TcFloatPrescale) {
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prescaleStep = true;
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}
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}
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// Keep the scale/offset in a few fp registers if we need it.
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if (prescaleStep) {
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LI(tempReg1, &gstate_c.uv);
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FL(32, prescaleRegs.scale.u, tempReg1, 0);
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FL(32, prescaleRegs.scale.v, tempReg1, 4);
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FL(32, prescaleRegs.offset.u, tempReg1, 8);
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FL(32, prescaleRegs.offset.v, tempReg1, 12);
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if ((dec.VertexType() & GE_VTYPE_TC_MASK) == GE_VTYPE_TC_8BIT) {
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LI(scratchReg, by128);
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FMV(FMv::W, FMv::X, fpScratchReg1, scratchReg);
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FMUL(32, prescaleRegs.scale.u, prescaleRegs.scale.u, fpScratchReg1);
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FMUL(32, prescaleRegs.scale.v, prescaleRegs.scale.v, fpScratchReg1);
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FMUL(32, prescaleRegs.offset.u, prescaleRegs.offset.u, fpScratchReg1);
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FMUL(32, prescaleRegs.offset.v, prescaleRegs.offset.v, fpScratchReg1);
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} else if ((dec.VertexType() & GE_VTYPE_TC_MASK) == GE_VTYPE_TC_16BIT) {
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LI(scratchReg, by32768);
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FMV(FMv::W, FMv::X, fpScratchReg1, scratchReg);
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FMUL(32, prescaleRegs.scale.u, prescaleRegs.scale.u, fpScratchReg1);
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FMUL(32, prescaleRegs.scale.v, prescaleRegs.scale.v, fpScratchReg1);
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FMUL(32, prescaleRegs.offset.u, prescaleRegs.offset.u, fpScratchReg1);
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FMUL(32, prescaleRegs.offset.v, prescaleRegs.offset.v, fpScratchReg1);
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}
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}
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if (dec.col) {
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// Or LDB and skip the conditional? This is probably cheaper.
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LI(fullAlphaReg, 0xFF);
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}
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if (dec.tc && dec.throughmode) {
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// TODO: Smarter, only when doing bounds.
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LI(tempReg1, &gstate_c.vertBounds.minU);
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LH(boundsMinUReg, tempReg1, offsetof(KnownVertexBounds, minU));
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LH(boundsMaxUReg, tempReg1, offsetof(KnownVertexBounds, maxU));
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LH(boundsMinVReg, tempReg1, offsetof(KnownVertexBounds, minV));
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LH(boundsMaxVReg, tempReg1, offsetof(KnownVertexBounds, maxV));
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}
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// TODO: Skipping, prescale.
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const u8 *loopStart = GetCodePtr();
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for (int i = 0; i < dec.numSteps_; i++) {
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if (!CompileStep(dec, i)) {
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EndWrite();
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// Reset the code ptr (effectively undoing what we generated) and return zero to indicate that we failed.
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ResetCodePtr(GetOffset(start));
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char temp[1024]{};
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dec.ToString(temp);
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ERROR_LOG(G3D, "Could not compile vertex decoder, failed at step %d: %s", i, temp);
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return nullptr;
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}
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}
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ADDI(srcReg, srcReg, dec.VertexSize());
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ADDI(dstReg, dstReg, dec.decFmt.stride);
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ADDI(counterReg, counterReg, -1);
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BLT(R_ZERO, counterReg, loopStart);
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if (dec.col) {
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LI(tempReg1, &gstate_c.vertexFullAlpha);
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FixupBranch skip = BNE(R_ZERO, fullAlphaReg);
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SB(fullAlphaReg, tempReg1, 0);
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SetJumpTarget(skip);
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}
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if (dec.tc && dec.throughmode) {
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// TODO: Smarter, only when doing bounds.
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LI(tempReg1, &gstate_c.vertBounds.minU);
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SH(boundsMinUReg, tempReg1, offsetof(KnownVertexBounds, minU));
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SH(boundsMaxUReg, tempReg1, offsetof(KnownVertexBounds, maxU));
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SH(boundsMinVReg, tempReg1, offsetof(KnownVertexBounds, minV));
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SH(boundsMaxVReg, tempReg1, offsetof(KnownVertexBounds, maxV));
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}
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RET();
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FlushIcache();
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if (log) {
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char temp[1024]{};
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dec.ToString(temp);
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INFO_LOG(JIT, "=== %s (%d bytes) ===", temp, (int)(GetCodePtr() - start));
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std::vector<std::string> lines = DisassembleRV64(start, (int)(GetCodePtr() - start));
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for (auto line : lines) {
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INFO_LOG(JIT, "%s", line.c_str());
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}
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INFO_LOG(JIT, "==========");
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}
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*jittedSize = (int)(GetCodePtr() - start);
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EndWrite();
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return (JittedVertexDecoder)start;
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}
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bool VertexDecoderJitCache::CompileStep(const VertexDecoder &dec, int step) {
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// See if we find a matching JIT function.
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for (size_t i = 0; i < ARRAY_SIZE(jitLookup); i++) {
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if (dec.steps_[step] == jitLookup[i].func) {
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((*this).*jitLookup[i].jitFunc)();
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return true;
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}
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}
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return false;
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}
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void VertexDecoderJitCache::Jit_TcU8ToFloat() {
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Jit_AnyU8ToFloat(dec_->tcoff, 16);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.uvoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_TcU16ToFloat() {
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Jit_AnyU16ToFloat(dec_->tcoff, 32);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.uvoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_TcFloat() {
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// Just copy 64 bits. Might be nice if we could detect misaligned load perf.
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LW(tempReg1, srcReg, dec_->tcoff);
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LW(tempReg2, srcReg, dec_->tcoff + 4);
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SW(tempReg1, dstReg, dec_->decFmt.uvoff);
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SW(tempReg2, dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_TcU16ThroughToFloat() {
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LHU(tempReg1, srcReg, dec_->tcoff + 0);
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LHU(tempReg2, srcReg, dec_->tcoff + 2);
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if (cpu_info.RiscV_B) {
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MINU(boundsMinUReg, boundsMinUReg, tempReg1);
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MAXU(boundsMaxUReg, boundsMaxUReg, tempReg1);
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MINU(boundsMinVReg, boundsMinVReg, tempReg2);
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MAXU(boundsMaxVReg, boundsMaxVReg, tempReg2);
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} else {
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auto updateSide = [&](RiscVReg src, bool greater, RiscVReg dst) {
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FixupBranch skip = BLT(greater ? dst : src, greater ? src : dst);
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MV(dst, src);
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SetJumpTarget(skip);
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};
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updateSide(tempReg1, false, boundsMinUReg);
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updateSide(tempReg1, true, boundsMaxUReg);
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updateSide(tempReg2, false, boundsMinVReg);
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updateSide(tempReg2, true, boundsMaxVReg);
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}
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FCVT(FConv::S, FConv::WU, fpSrc[0], tempReg1, Round::TOZERO);
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FCVT(FConv::S, FConv::WU, fpSrc[1], tempReg2, Round::TOZERO);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.uvoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_TcFloatThrough() {
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// Just copy 64 bits. Might be nice if we could detect misaligned load perf.
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LW(tempReg1, srcReg, dec_->tcoff);
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LW(tempReg2, srcReg, dec_->tcoff + 4);
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SW(tempReg1, dstReg, dec_->decFmt.uvoff);
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SW(tempReg2, dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_TcU8Prescale() {
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LBU(tempReg1, srcReg, dec_->tcoff + 0);
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LBU(tempReg2, srcReg, dec_->tcoff + 1);
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FCVT(FConv::S, FConv::WU, fpSrc[0], tempReg1, Round::TOZERO);
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FCVT(FConv::S, FConv::WU, fpSrc[1], tempReg2, Round::TOZERO);
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FMADD(32, fpSrc[0], fpSrc[0], prescaleRegs.scale.u, prescaleRegs.offset.u);
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FMADD(32, fpSrc[1], fpSrc[1], prescaleRegs.scale.v, prescaleRegs.offset.v);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.uvoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_TcU16Prescale() {
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LHU(tempReg1, srcReg, dec_->tcoff + 0);
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LHU(tempReg2, srcReg, dec_->tcoff + 2);
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FCVT(FConv::S, FConv::WU, fpSrc[0], tempReg1, Round::TOZERO);
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FCVT(FConv::S, FConv::WU, fpSrc[1], tempReg2, Round::TOZERO);
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FMADD(32, fpSrc[0], fpSrc[0], prescaleRegs.scale.u, prescaleRegs.offset.u);
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FMADD(32, fpSrc[1], fpSrc[1], prescaleRegs.scale.v, prescaleRegs.offset.v);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.uvoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_TcFloatPrescale() {
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FL(32, fpSrc[0], srcReg, dec_->tcoff + 0);
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FL(32, fpSrc[1], srcReg, dec_->tcoff + 4);
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FMADD(32, fpSrc[0], fpSrc[0], prescaleRegs.scale.u, prescaleRegs.offset.u);
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FMADD(32, fpSrc[1], fpSrc[1], prescaleRegs.scale.v, prescaleRegs.offset.v);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.uvoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.uvoff + 4);
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}
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void VertexDecoderJitCache::Jit_NormalS8() {
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LB(tempReg1, srcReg, dec_->nrmoff);
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LB(tempReg2, srcReg, dec_->nrmoff + 1);
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LB(tempReg3, srcReg, dec_->nrmoff + 2);
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SB(tempReg1, dstReg, dec_->decFmt.nrmoff);
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SB(tempReg2, dstReg, dec_->decFmt.nrmoff + 1);
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SB(tempReg3, dstReg, dec_->decFmt.nrmoff + 2);
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SB(R_ZERO, dstReg, dec_->decFmt.nrmoff + 3);
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}
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void VertexDecoderJitCache::Jit_NormalS16() {
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LH(tempReg1, srcReg, dec_->nrmoff);
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LH(tempReg2, srcReg, dec_->nrmoff + 2);
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LH(tempReg3, srcReg, dec_->nrmoff + 4);
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SH(tempReg1, dstReg, dec_->decFmt.nrmoff);
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SH(tempReg2, dstReg, dec_->decFmt.nrmoff + 2);
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SH(tempReg3, dstReg, dec_->decFmt.nrmoff + 4);
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SH(R_ZERO, dstReg, dec_->decFmt.nrmoff + 6);
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}
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void VertexDecoderJitCache::Jit_NormalFloat() {
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// Just copy 12 bytes, play with over read/write later.
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LW(tempReg1, srcReg, dec_->nrmoff);
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LW(tempReg2, srcReg, dec_->nrmoff + 4);
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LW(tempReg3, srcReg, dec_->nrmoff + 8);
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SW(tempReg1, dstReg, dec_->decFmt.nrmoff);
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SW(tempReg2, dstReg, dec_->decFmt.nrmoff + 4);
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SW(tempReg3, dstReg, dec_->decFmt.nrmoff + 8);
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}
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void VertexDecoderJitCache::Jit_PosS8() {
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Jit_AnyS8ToFloat(dec_->posoff);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.posoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.posoff + 4);
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FS(32, fpSrc[2], dstReg, dec_->decFmt.posoff + 8);
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}
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void VertexDecoderJitCache::Jit_PosS16() {
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Jit_AnyS16ToFloat(dec_->posoff);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.posoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.posoff + 4);
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FS(32, fpSrc[2], dstReg, dec_->decFmt.posoff + 8);
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}
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void VertexDecoderJitCache::Jit_PosFloat() {
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// Just copy 12 bytes, play with over read/write later.
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LW(tempReg1, srcReg, dec_->posoff);
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LW(tempReg2, srcReg, dec_->posoff + 4);
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LW(tempReg3, srcReg, dec_->posoff + 8);
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SW(tempReg1, dstReg, dec_->decFmt.posoff);
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SW(tempReg2, dstReg, dec_->decFmt.posoff + 4);
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SW(tempReg3, dstReg, dec_->decFmt.posoff + 8);
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}
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void VertexDecoderJitCache::Jit_PosS8Through() {
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// 8-bit positions in throughmode always decode to 0, depth included.
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SW(R_ZERO, dstReg, dec_->decFmt.posoff);
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SW(R_ZERO, dstReg, dec_->decFmt.posoff + 4);
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SW(R_ZERO, dstReg, dec_->decFmt.posoff + 8);
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}
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void VertexDecoderJitCache::Jit_PosS16Through() {
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// Start with X and Y (which are signed.)
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LH(tempReg1, srcReg, dec_->posoff + 0);
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LH(tempReg2, srcReg, dec_->posoff + 2);
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// This one, Z, has to be unsigned.
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LHU(tempReg3, srcReg, dec_->posoff + 4);
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FCVT(FConv::S, FConv::WU, fpSrc[0], tempReg1, Round::TOZERO);
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FCVT(FConv::S, FConv::WU, fpSrc[1], tempReg2, Round::TOZERO);
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FCVT(FConv::S, FConv::WU, fpSrc[2], tempReg3, Round::TOZERO);
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FS(32, fpSrc[0], dstReg, dec_->decFmt.posoff);
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FS(32, fpSrc[1], dstReg, dec_->decFmt.posoff + 4);
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FS(32, fpSrc[2], dstReg, dec_->decFmt.posoff + 8);
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}
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void VertexDecoderJitCache::Jit_PosFloatThrough() {
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// Start by copying 8 bytes, then handle Z separately to clamp it.
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LW(tempReg1, srcReg, dec_->posoff);
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LW(tempReg2, srcReg, dec_->posoff + 4);
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|
FL(32, fpSrc[2], srcReg, dec_->posoff + 8);
|
|
SW(tempReg1, dstReg, dec_->decFmt.posoff);
|
|
SW(tempReg2, dstReg, dec_->decFmt.posoff + 4);
|
|
|
|
// Load the constants to clamp. Maybe could static alloc this constant in a reg.
|
|
LI(scratchReg, const65535);
|
|
FMV(FMv::W, FMv::X, fpScratchReg1, R_ZERO);
|
|
FMV(FMv::W, FMv::X, fpScratchReg2, scratchReg);
|
|
|
|
FMAX(32, fpSrc[2], fpSrc[2], fpScratchReg1);
|
|
FMIN(32, fpSrc[2], fpSrc[2], fpScratchReg2);
|
|
FS(32, fpSrc[2], dstReg, dec_->decFmt.posoff + 8);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_Color8888() {
|
|
LW(tempReg1, srcReg, dec_->coloff);
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|
|
|
// Set tempReg2=-1 if full alpha, 0 otherwise.
|
|
SRLI(tempReg2, tempReg1, 24);
|
|
SLTIU(tempReg2, tempReg2, 0xFF);
|
|
ADDI(tempReg2, tempReg2, -1);
|
|
|
|
// Now use that as a mask to clear fullAlpha.
|
|
AND(fullAlphaReg, fullAlphaReg, tempReg2);
|
|
|
|
SW(tempReg1, dstReg, dec_->decFmt.c0off);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_Color4444() {
|
|
LHU(tempReg1, srcReg, dec_->coloff);
|
|
|
|
// Red...
|
|
ANDI(tempReg2, tempReg1, 0x0F);
|
|
// Move green left to position 8.
|
|
ANDI(tempReg3, tempReg1, 0xF0);
|
|
SLLI(tempReg3, tempReg3, 4);
|
|
OR(tempReg2, tempReg2, tempReg3);
|
|
// For blue, we modify tempReg1 since immediates are sign extended after 11 bits.
|
|
SRLI(tempReg1, tempReg1, 8);
|
|
ANDI(tempReg3, tempReg1, 0x0F);
|
|
SLLI(tempReg3, tempReg3, 16);
|
|
OR(tempReg2, tempReg2, tempReg3);
|
|
// And now alpha, moves 20 to get to 24.
|
|
ANDI(tempReg3, tempReg1, 0xF0);
|
|
SLLI(tempReg3, tempReg3, 20);
|
|
OR(tempReg2, tempReg2, tempReg3);
|
|
|
|
// Now we swizzle.
|
|
SLLI(tempReg3, tempReg2, 4);
|
|
OR(tempReg2, tempReg2, tempReg3);
|
|
|
|
// Color is down, now let's say the fullAlphaReg flag from tempReg1 (still has alpha.)
|
|
// Set tempReg1=-1 if full alpha, 0 otherwise.
|
|
SLTIU(tempReg1, tempReg1, 0xF0);
|
|
ADDI(tempReg1, tempReg1, -1);
|
|
|
|
// Now use that as a mask to clear fullAlpha.
|
|
AND(fullAlphaReg, fullAlphaReg, tempReg1);
|
|
|
|
SW(tempReg2, dstReg, dec_->decFmt.c0off);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_Color565() {
|
|
LHU(tempReg1, srcReg, dec_->coloff);
|
|
|
|
// Start by extracting green.
|
|
SRLI(tempReg2, tempReg1, 5);
|
|
ANDI(tempReg2, tempReg2, 0x3F);
|
|
// And now swizzle 6 -> 8, using a wall to clear bits.
|
|
SRLI(tempReg3, tempReg2, 4);
|
|
SLLI(tempReg3, tempReg3, 8);
|
|
SLLI(tempReg2, tempReg2, 2 + 8);
|
|
OR(tempReg2, tempReg2, tempReg3);
|
|
|
|
// Now pull blue out using a wall to isolate it.
|
|
SRLI(tempReg3, tempReg1, 11);
|
|
// And now isolate red and combine them.
|
|
ANDI(tempReg1, tempReg1, 0x1F);
|
|
SLLI(tempReg3, tempReg3, 16);
|
|
OR(tempReg1, tempReg1, tempReg3);
|
|
// Now we swizzle them together.
|
|
SRLI(tempReg3, tempReg1, 2);
|
|
SLLI(tempReg1, tempReg1, 3);
|
|
OR(tempReg1, tempReg1, tempReg3);
|
|
// But we have to clear the bits now which is annoying.
|
|
LI(tempReg3, 0x00FF00FF);
|
|
AND(tempReg1, tempReg1, tempReg3);
|
|
|
|
// Now add green back in, and then make an alpha FF and add it too.
|
|
OR(tempReg1, tempReg1, tempReg2);
|
|
LI(tempReg3, (s32)0xFF000000);
|
|
OR(tempReg1, tempReg1, tempReg3);
|
|
|
|
SW(tempReg1, dstReg, dec_->decFmt.c0off);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_Color5551() {
|
|
LHU(tempReg1, srcReg, dec_->coloff);
|
|
|
|
// Separate each color.
|
|
SRLI(tempReg2, tempReg1, 5);
|
|
SRLI(tempReg3, tempReg1, 10);
|
|
|
|
// Set tempReg3 to -1 if the alpha bit is set.
|
|
SLLIW(scratchReg, tempReg1, 16);
|
|
SRAIW(scratchReg, scratchReg, 31);
|
|
// Now we can mask the flag.
|
|
AND(fullAlphaReg, fullAlphaReg, scratchReg);
|
|
|
|
// Let's move alpha into position.
|
|
SLLI(scratchReg, scratchReg, 24);
|
|
|
|
// Mask each.
|
|
ANDI(tempReg1, tempReg1, 0x1F);
|
|
ANDI(tempReg2, tempReg2, 0x1F);
|
|
ANDI(tempReg3, tempReg3, 0x1F);
|
|
// And shift into position.
|
|
SLLI(tempReg2, tempReg2, 8);
|
|
SLLI(tempReg3, tempReg3, 16);
|
|
// Combine RGB together.
|
|
OR(tempReg1, tempReg1, tempReg2);
|
|
OR(tempReg1, tempReg1, tempReg3);
|
|
// Swizzle our 5 -> 8
|
|
SRLI(tempReg2, tempReg1, 2);
|
|
SLLI(tempReg1, tempReg1, 3);
|
|
// Mask out the overflow in tempReg2 and combine.
|
|
LI(tempReg3, 0x00070707);
|
|
AND(tempReg2, tempReg2, tempReg3);
|
|
OR(tempReg1, tempReg1, tempReg2);
|
|
|
|
// Add in alpha and we're done.
|
|
OR(tempReg1, tempReg1, scratchReg);
|
|
|
|
SW(tempReg1, dstReg, dec_->decFmt.c0off);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_AnyS8ToFloat(int srcoff) {
|
|
LB(tempReg1, srcReg, srcoff + 0);
|
|
LB(tempReg2, srcReg, srcoff + 1);
|
|
LB(tempReg3, srcReg, srcoff + 2);
|
|
// TODO: Could maybe static alloc?
|
|
LI(scratchReg, by128);
|
|
FMV(FMv::W, FMv::X, fpScratchReg1, scratchReg);
|
|
FCVT(FConv::S, FConv::W, fpSrc[0], tempReg1, Round::TOZERO);
|
|
FCVT(FConv::S, FConv::W, fpSrc[1], tempReg2, Round::TOZERO);
|
|
FCVT(FConv::S, FConv::W, fpSrc[2], tempReg3, Round::TOZERO);
|
|
FMUL(32, fpSrc[0], fpSrc[0], fpScratchReg1);
|
|
FMUL(32, fpSrc[1], fpSrc[1], fpScratchReg1);
|
|
FMUL(32, fpSrc[2], fpSrc[2], fpScratchReg1);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_AnyS16ToFloat(int srcoff) {
|
|
LH(tempReg1, srcReg, srcoff + 0);
|
|
LH(tempReg2, srcReg, srcoff + 2);
|
|
LH(tempReg3, srcReg, srcoff + 4);
|
|
// TODO: Could maybe static alloc?
|
|
LI(scratchReg, by32768);
|
|
FMV(FMv::W, FMv::X, fpScratchReg1, scratchReg);
|
|
FCVT(FConv::S, FConv::W, fpSrc[0], tempReg1, Round::TOZERO);
|
|
FCVT(FConv::S, FConv::W, fpSrc[1], tempReg2, Round::TOZERO);
|
|
FCVT(FConv::S, FConv::W, fpSrc[2], tempReg3, Round::TOZERO);
|
|
FMUL(32, fpSrc[0], fpSrc[0], fpScratchReg1);
|
|
FMUL(32, fpSrc[1], fpSrc[1], fpScratchReg1);
|
|
FMUL(32, fpSrc[2], fpSrc[2], fpScratchReg1);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_AnyU8ToFloat(int srcoff, u32 bits) {
|
|
_dbg_assert_msg_((bits & ~(16 | 8)) == 0, "Bits must be a multiple of 8.");
|
|
_dbg_assert_msg_(bits >= 8 && bits <= 24, "Bits must be a between 8 and 24.");
|
|
|
|
LBU(tempReg1, srcReg, srcoff + 0);
|
|
if (bits >= 16)
|
|
LBU(tempReg2, srcReg, srcoff + 1);
|
|
if (bits >= 24)
|
|
LBU(tempReg3, srcReg, srcoff + 2);
|
|
// TODO: Could maybe static alloc?
|
|
LI(scratchReg, by128);
|
|
FMV(FMv::W, FMv::X, fpScratchReg1, scratchReg);
|
|
FCVT(FConv::S, FConv::WU, fpSrc[0], tempReg1, Round::TOZERO);
|
|
if (bits >= 16)
|
|
FCVT(FConv::S, FConv::WU, fpSrc[1], tempReg2, Round::TOZERO);
|
|
if (bits >= 24)
|
|
FCVT(FConv::S, FConv::WU, fpSrc[2], tempReg3, Round::TOZERO);
|
|
FMUL(32, fpSrc[0], fpSrc[0], fpScratchReg1);
|
|
if (bits >= 16)
|
|
FMUL(32, fpSrc[1], fpSrc[1], fpScratchReg1);
|
|
if (bits >= 24)
|
|
FMUL(32, fpSrc[2], fpSrc[2], fpScratchReg1);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_AnyU16ToFloat(int srcoff, u32 bits) {
|
|
_dbg_assert_msg_((bits & ~(32 | 16)) == 0, "Bits must be a multiple of 16.");
|
|
_dbg_assert_msg_(bits >= 16 && bits <= 48, "Bits must be a between 16 and 48.");
|
|
|
|
LHU(tempReg1, srcReg, srcoff + 0);
|
|
if (bits >= 32)
|
|
LHU(tempReg2, srcReg, srcoff + 2);
|
|
if (bits >= 48)
|
|
LHU(tempReg3, srcReg, srcoff + 4);
|
|
// TODO: Could maybe static alloc?
|
|
LI(scratchReg, by32768);
|
|
FMV(FMv::W, FMv::X, fpScratchReg1, scratchReg);
|
|
FCVT(FConv::S, FConv::WU, fpSrc[0], tempReg1, Round::TOZERO);
|
|
if (bits >= 32)
|
|
FCVT(FConv::S, FConv::WU, fpSrc[1], tempReg2, Round::TOZERO);
|
|
if (bits >= 48)
|
|
FCVT(FConv::S, FConv::WU, fpSrc[2], tempReg3, Round::TOZERO);
|
|
FMUL(32, fpSrc[0], fpSrc[0], fpScratchReg1);
|
|
if (bits >= 32)
|
|
FMUL(32, fpSrc[1], fpSrc[1], fpScratchReg1);
|
|
if (bits >= 48)
|
|
FMUL(32, fpSrc[2], fpSrc[2], fpScratchReg1);
|
|
}
|
|
|
|
#endif // PPSSPP_ARCH(RISCV64)
|