Henrik RydgårdandClaude Opus 5.5 d7e449ab75 ARM JIT: Fix ins with msb below pos, ext past bit 31, and constant max/min ...

ins with msb below pos encoded an invalid BFI instead of doing nothing,
as the interpreter and the other JITs do, and ext with pos + size past 32
an invalid UBFX. max and min of two constants compared them unsigned.
Found by CPUEquivalence.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

2026-10-14 12:29:49 +02:00

..

ArmAsm.cpp

Keep JIT block entries and replacement hooks out of PSP memory

2026-10-11 10:33:30 +02:00

ArmCompALU.cpp

ARM JIT: Fix ins with msb below pos, ext past bit 31, and constant max/min

2026-10-14 12:29:49 +02:00

ArmCompBranch.cpp

Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.

2026-08-15 19:14:13 +02:00

ArmCompFPU.cpp

ARM JIT: Keep the guest's flush-to-zero in round, ceil and floor

2026-10-14 09:38:29 +02:00

ArmCompLoadStore.cpp

Core: Let 16-bit CPU accesses through the depth mirrors see the GE's layout

2026-10-08 18:37:23 +02:00

ArmCompReplace.cpp

cmake: Detect features at compile time

2016-10-19 12:31:19 +02:00

ArmCompVFPU.cpp

VFPU: vcmov with imm3 = 7 tests a CC bit that is always clear

2026-10-14 11:59:35 +02:00

ArmJit.cpp

JITs: Notice a rounding mode that didn't come from a compiled ctc1

2026-10-14 09:26:28 +02:00

ArmJit.h

ARM JIT: Keep the guest's flush-to-zero in round, ceil and floor

2026-10-14 09:38:29 +02:00

ArmRegCache.cpp

Remove more vestiges of old experiments

2026-02-12 01:23:48 +01:00

ArmRegCache.h

Remove more vestiges of old experiments

2026-02-12 01:23:48 +01:00

ArmRegCacheFPU.cpp

mips/regcache: fix before check index after access data array by index

2026-04-28 10:55:55 +02:00

ArmRegCacheFPU.h

VFPU: vsqrt, vrsq, vrcp and vnrcp are exact in every backend

2026-09-24 12:24:42 -06:00