Henrik RydgårdandClaude Opus 5.5 657e99fcbf ME: Let kernel code on the main CPU reach RAM and VRAM through kseg1 ...

Yabause-PSP's me.prx ORs 0xA0000000 onto its own addresses to share a
buffer with the ME uncached, which is 0xA8xxxxxx for a module in kernel
RAM. The main CPU's space has no views there, so it crashed.

All of kernel segment 1 (0xA0000000-0xBFFFFFFF) now counts as MMIO, and a
device below the hardware registers maps RAM and VRAM onto their uncached
mirrors at 0x40000000. The main CPU's native kernel loads and stores send
the whole segment to that path; the ME keeps 0xBC000000 as the boundary,
since its space maps the rest.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-10-21 12:50:46 +02:00

..

Arm64IRAsm.cpp

ME: Run the Media Engine on the ARM64 and x64 JITs

2026-10-21 10:28:50 +02:00

Arm64IRCompALU.cpp

arm64 IR JIT: divu by zero compared the numerator signed

2026-09-22 11:02:20 -06:00

Arm64IRCompBranch.cpp

CPU: Give each MIPSState an address space for its memory accesses

2026-10-20 18:41:28 +02:00

Arm64IRCompFPU.cpp

VFPU: vmin and vmax order zeros and denormals as equal, on every core

2026-10-14 11:59:35 +02:00

Arm64IRCompLoadStore.cpp

ME: Let kernel code on the main CPU reach RAM and VRAM through kseg1

2026-10-21 12:50:46 +02:00

Arm64IRCompSystem.cpp

HLE: Pass the MIPSState to syscalls and their implementations

2026-10-20 15:45:14 +02:00

Arm64IRCompVec.cpp

VFPU: Drop the inaccurate dot product paths

2026-10-18 12:11:46 +02:00

Arm64IRJit.cpp

ME: Run the Media Engine on the ARM64 and x64 JITs

2026-10-21 10:28:50 +02:00

Arm64IRJit.h

ME: Run the Media Engine on the ARM64 and x64 JITs

2026-10-21 10:28:50 +02:00

Arm64IRRegCache.cpp

CPU: Give each MIPSState an address space for its memory accesses

2026-10-20 18:41:28 +02:00

Arm64IRRegCache.h

ARM64 IR JIT: Join two mapped pairs into a quad with a ZIP1

2026-10-15 11:02:17 +02:00

Arm64VfpuDot.h

IR: Compute runs of VFPU dot products four at a time

2026-10-15 11:02:17 +02:00