mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-12 05:50:29 +02:00
442 lines
11 KiB
C++
442 lines
11 KiB
C++
#include "Common/Log.h"
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#include "Core/MIPS/IR/IRPassSimplify.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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u32 Evaluate(u32 a, u32 b, IROp op) {
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switch (op) {
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case IROp::Add: case IROp::AddConst: return a + b;
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case IROp::Sub: case IROp::SubConst: return a - b;
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case IROp::And: case IROp::AndConst: return a & b;
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case IROp::Or: case IROp::OrConst: return a | b;
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case IROp::Xor: case IROp::XorConst: return a ^ b;
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case IROp::Shr: case IROp::ShrImm: return a >> b;
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case IROp::Sar: case IROp::SarImm: return (s32)a >> b;
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case IROp::Ror: case IROp::RorImm: return (a >> b) | (a << (32 - b));
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case IROp::Shl: case IROp::ShlImm: return a << b;
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case IROp::Slt: case IROp::SltConst: return ((s32)a < (s32)b);
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case IROp::SltU: case IROp::SltUConst: return (a < b);
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default:
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return -1;
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}
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}
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u32 Evaluate(u32 a, IROp op) {
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switch (op) {
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case IROp::Not: return ~a;
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case IROp::Neg: return -(s32)a;
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case IROp::BSwap16: return ((a & 0xFF00FF00) >> 8) | ((a & 0x00FF00FF) << 8);
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case IROp::BSwap32: return swap32(a);
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case IROp::Ext8to32: return (u32)(s32)(s8)(u8)a;
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case IROp::Ext16to32: return (u32)(s32)(s16)(u16)a;
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case IROp::Clz: {
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int x = 31;
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int count = 0;
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while (x >= 0 && !(a & (1 << x))) {
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count++;
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x--;
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}
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return count;
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}
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default:
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return -1;
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}
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}
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IROp ArithToArithConst(IROp op) {
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switch (op) {
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case IROp::Add: return IROp::AddConst;
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case IROp::Sub: return IROp::SubConst;
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case IROp::And: return IROp::AndConst;
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case IROp::Or: return IROp::OrConst;
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case IROp::Xor: return IROp::XorConst;
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case IROp::Slt: return IROp::SltConst;
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case IROp::SltU: return IROp::SltUConst;
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default:
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return (IROp)-1;
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}
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}
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IROp ShiftToShiftImm(IROp op) {
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switch (op) {
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case IROp::Shl: return IROp::ShlImm;
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case IROp::Shr: return IROp::ShrImm;
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case IROp::Ror: return IROp::RorImm;
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case IROp::Sar: return IROp::SarImm;
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default:
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return (IROp)-1;
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}
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}
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bool IRApplyPasses(const IRPassFunc *passes, size_t c, const IRWriter &in, IRWriter &out) {
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if (c == 1) {
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return passes[0](in, out);
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}
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bool logBlocks = false;
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IRWriter temp[2];
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const IRWriter *nextIn = ∈
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IRWriter *nextOut = &temp[1];
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for (size_t i = 0; i < c - 1; ++i) {
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if (passes[i](*nextIn, *nextOut)) {
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logBlocks = true;
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}
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temp[0] = std::move(temp[1]);
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nextIn = &temp[0];
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}
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if (passes[c - 1](*nextIn, out)) {
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logBlocks = true;
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}
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return logBlocks;
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}
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bool PropagateConstants(const IRWriter &in, IRWriter &out) {
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IRRegCache gpr(&out);
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const u32 *constants = in.GetConstants().data();
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bool logBlocks = false;
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for (int i = 0; i < (int)in.GetInstructions().size(); i++) {
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IRInst inst = in.GetInstructions()[i];
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bool symmetric = true;
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if (out.GetConstants().size() > 128) {
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// Avoid causing a constant explosion.
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goto doDefaultAndFlush;
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}
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switch (inst.op) {
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case IROp::SetConst:
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gpr.SetImm(inst.dest, constants[inst.src1]);
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break;
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case IROp::SetConstF:
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goto doDefault;
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case IROp::Sub:
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case IROp::Slt:
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case IROp::SltU:
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symmetric = false; // fallthrough
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case IROp::Add:
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case IROp::And:
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case IROp::Or:
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case IROp::Xor:
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// Regularize, for the add/or check below.
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if (symmetric && inst.src2 == inst.dest && inst.src1 != inst.src2) {
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std::swap(inst.src1, inst.src2);
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}
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if (gpr.IsImm(inst.src1) && gpr.IsImm(inst.src2)) {
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gpr.SetImm(inst.dest, Evaluate(gpr.GetImm(inst.src1), gpr.GetImm(inst.src2), inst.op));
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} else if (gpr.IsImm(inst.src2)) {
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const u32 imm2 = gpr.GetImm(inst.src2);
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gpr.MapDirtyIn(inst.dest, inst.src1);
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if (imm2 == 0 && (inst.op == IROp::Add || inst.op == IROp::Or)) {
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// Add / Or with zero is just a Mov.
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if (inst.dest != inst.src1)
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out.Write(IROp::Mov, inst.dest, inst.src1);
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} else {
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out.Write(ArithToArithConst(inst.op), inst.dest, inst.src1, out.AddConstant(imm2));
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}
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} else if (symmetric && gpr.IsImm(inst.src1)) {
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const u32 imm1 = gpr.GetImm(inst.src1);
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gpr.MapDirtyIn(inst.dest, inst.src2);
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if (imm1 == 0 && (inst.op == IROp::Add || inst.op == IROp::Or)) {
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// Add / Or with zero is just a Mov.
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if (inst.dest != inst.src2)
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out.Write(IROp::Mov, inst.dest, inst.src2);
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} else {
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out.Write(ArithToArithConst(inst.op), inst.dest, inst.src2, out.AddConstant(imm1));
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}
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} else {
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gpr.MapDirtyInIn(inst.dest, inst.src1, inst.src2);
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goto doDefault;
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}
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break;
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case IROp::Neg:
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case IROp::Not:
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case IROp::BSwap16:
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case IROp::BSwap32:
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case IROp::Ext8to32:
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case IROp::Ext16to32:
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case IROp::Clz:
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if (gpr.IsImm(inst.src1)) {
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gpr.SetImm(inst.dest, Evaluate(gpr.GetImm(inst.src1), inst.op));
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} else {
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gpr.MapDirtyIn(inst.dest, inst.src1);
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goto doDefault;
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}
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break;
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case IROp::AddConst:
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case IROp::SubConst:
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case IROp::AndConst:
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case IROp::OrConst:
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case IROp::XorConst:
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case IROp::SltConst:
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case IROp::SltUConst:
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if (gpr.IsImm(inst.src1)) {
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gpr.SetImm(inst.dest, Evaluate(gpr.GetImm(inst.src1), constants[inst.src2], inst.op));
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} else {
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gpr.MapDirtyIn(inst.dest, inst.src1);
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goto doDefault;
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}
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break;
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case IROp::Shl:
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case IROp::Shr:
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case IROp::Ror:
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case IROp::Sar:
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if (gpr.IsImm(inst.src1) && gpr.IsImm(inst.src2)) {
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gpr.SetImm(inst.dest, Evaluate(gpr.GetImm(inst.src1), gpr.GetImm(inst.src2), inst.op));
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} else if (gpr.IsImm(inst.src2)) {
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const u8 sa = gpr.GetImm(inst.src2) & 31;
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gpr.MapDirtyIn(inst.dest, inst.src1);
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if (sa == 0) {
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if (inst.dest != inst.src1)
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out.Write(IROp::Mov, inst.dest, inst.src1);
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} else {
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out.Write(ShiftToShiftImm(inst.op), inst.dest, inst.src1, sa);
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}
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} else {
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gpr.MapDirtyInIn(inst.dest, inst.src1, inst.src2);
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goto doDefault;
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}
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break;
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case IROp::ShlImm:
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case IROp::ShrImm:
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case IROp::RorImm:
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case IROp::SarImm:
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if (gpr.IsImm(inst.src1)) {
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gpr.SetImm(inst.dest, Evaluate(gpr.GetImm(inst.src1), inst.src2, inst.op));
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} else {
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gpr.MapDirtyIn(inst.dest, inst.src1);
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goto doDefault;
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}
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break;
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case IROp::Mov:
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if (inst.dest == inst.src1) {
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// Nop
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} else if (gpr.IsImm(inst.src1)) {
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gpr.SetImm(inst.dest, gpr.GetImm(inst.src1));
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} else {
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gpr.MapDirtyIn(inst.dest, inst.src1);
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goto doDefault;
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}
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break;
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case IROp::Mult:
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case IROp::MultU:
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gpr.MapInIn(inst.src1, inst.src2);
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goto doDefault;
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case IROp::MovZ:
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case IROp::MovNZ:
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gpr.MapInInIn(inst.dest, inst.src1, inst.src2);
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goto doDefault;
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case IROp::Min:
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case IROp::Max:
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gpr.MapDirtyInIn(inst.dest, inst.src1, inst.src2);
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goto doDefault;
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case IROp::FMovFromGPR:
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if (gpr.IsImm(inst.src1)) {
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out.Write(IROp::SetConstF, inst.dest, out.AddConstant(gpr.GetImm(inst.src1)));
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} else {
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gpr.MapIn(inst.src1);
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goto doDefault;
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}
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break;
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case IROp::FMovToGPR:
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gpr.MapDirty(inst.dest);
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goto doDefault;
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case IROp::MfHi:
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case IROp::MfLo:
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gpr.MapDirty(inst.dest);
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goto doDefault;
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case IROp::MtHi:
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case IROp::MtLo:
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gpr.MapIn(inst.src1);
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goto doDefault;
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case IROp::Store8:
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case IROp::Store16:
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case IROp::Store32:
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if (gpr.IsImm(inst.src1) && inst.src1 != inst.dest) {
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gpr.MapIn(inst.dest);
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out.Write(inst.op, inst.dest, 0, out.AddConstant(gpr.GetImm(inst.src1) + constants[inst.src2]));
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} else {
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gpr.MapInIn(inst.dest, inst.src1);
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goto doDefault;
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}
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break;
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case IROp::StoreFloat:
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case IROp::StoreVec4:
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if (gpr.IsImm(inst.src1)) {
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out.Write(inst.op, inst.dest, 0, out.AddConstant(gpr.GetImm(inst.src1) + constants[inst.src2]));
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} else {
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gpr.MapIn(inst.src1);
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goto doDefault;
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}
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break;
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case IROp::Load8:
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case IROp::Load8Ext:
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case IROp::Load16:
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case IROp::Load16Ext:
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case IROp::Load32:
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if (gpr.IsImm(inst.src1) && inst.src1 != inst.dest) {
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gpr.MapDirty(inst.dest);
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out.Write(inst.op, inst.dest, 0, out.AddConstant(gpr.GetImm(inst.src1) + constants[inst.src2]));
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} else {
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gpr.MapDirtyIn(inst.dest, inst.src1);
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goto doDefault;
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}
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break;
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case IROp::LoadFloat:
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case IROp::LoadVec4:
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if (gpr.IsImm(inst.src1)) {
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out.Write(inst.op, inst.dest, 0, out.AddConstant(gpr.GetImm(inst.src1) + constants[inst.src2]));
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} else {
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gpr.MapIn(inst.src1);
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goto doDefault;
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}
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break;
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case IROp::Downcount:
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case IROp::SetPCConst:
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goto doDefault;
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case IROp::SetPC:
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if (gpr.IsImm(inst.src1)) {
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out.Write(IROp::SetPCConst, out.AddConstant(gpr.GetImm(inst.src1)));
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} else {
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gpr.MapIn(inst.src1);
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goto doDefault;
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}
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break;
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// FP-only instructions don't need to flush immediates.
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case IROp::FAdd:
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case IROp::FMul:
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// Regularize, to help x86 backends (add.s r0, r1, r0 -> add.s r0, r0, r1)
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if (inst.src2 == inst.dest && inst.src1 != inst.src2)
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std::swap(inst.src1, inst.src2);
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out.Write(inst);
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break;
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case IROp::FSub:
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case IROp::FDiv:
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case IROp::FNeg:
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case IROp::FAbs:
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case IROp::FMov:
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case IROp::FRound:
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case IROp::FTrunc:
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case IROp::FCeil:
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case IROp::FFloor:
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case IROp::FCvtSW:
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case IROp::FSin:
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case IROp::FCos:
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case IROp::FSqrt:
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case IROp::FRSqrt:
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case IROp::FRecip:
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case IROp::FAsin:
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out.Write(inst);
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break;
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case IROp::SetCtrlVFPU:
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goto doDefault;
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case IROp::FCvtWS:
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// TODO: Actually, this should just use the currently set rounding mode.
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// Move up with FCvtSW when that's implemented.
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gpr.MapIn(IRREG_FCR31);
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out.Write(inst);
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break;
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case IROp::FpCondToReg:
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if (gpr.IsImm(IRREG_FPCOND)) {
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gpr.SetImm(inst.dest, gpr.GetImm(IRREG_FPCOND));
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} else {
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gpr.MapDirtyIn(inst.dest, IRREG_FPCOND);
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out.Write(inst);
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}
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break;
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case IROp::Vec4Init:
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case IROp::Vec4Add:
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case IROp::Vec4Sub:
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case IROp::Vec4Mul:
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case IROp::Vec4Div:
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case IROp::Vec4Scale:
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case IROp::Vec4Shuffle:
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out.Write(inst);
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break;
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case IROp::ZeroFpCond:
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case IROp::FCmpUnordered:
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case IROp::FCmpEqual:
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case IROp::FCmpEqualUnordered:
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case IROp::FCmpLessOrdered:
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case IROp::FCmpLessUnordered:
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case IROp::FCmpLessEqualOrdered:
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case IROp::FCmpLessEqualUnordered:
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gpr.MapDirty(IRREG_FPCOND);
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goto doDefault;
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case IROp::RestoreRoundingMode:
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case IROp::ApplyRoundingMode:
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case IROp::UpdateRoundingMode:
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goto doDefault;
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case IROp::VfpuCtrlToReg:
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gpr.MapDirtyIn(inst.dest, IRREG_VFPU_CTRL_BASE + inst.src1);
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goto doDefault;
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case IROp::Syscall:
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case IROp::Interpret:
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case IROp::ExitToConst:
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case IROp::ExitToReg:
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case IROp::ExitToConstIfEq:
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case IROp::ExitToConstIfNeq:
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case IROp::ExitToConstIfFpFalse:
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case IROp::ExitToConstIfFpTrue:
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case IROp::ExitToConstIfGeZ:
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case IROp::ExitToConstIfGtZ:
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case IROp::ExitToConstIfLeZ:
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case IROp::ExitToConstIfLtZ:
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default:
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{
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doDefaultAndFlush:
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gpr.FlushAll();
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doDefault:
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// Remap constants to the new reality
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const IRMeta *m = GetIRMeta(inst.op);
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switch (m->types[0]) {
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case 'C':
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inst.dest = out.AddConstant(constants[inst.dest]);
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break;
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}
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switch (m->types[1]) {
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case 'C':
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inst.src1 = out.AddConstant(constants[inst.src1]);
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break;
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}
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switch (m->types[2]) {
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case 'C':
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inst.src2 = out.AddConstant(constants[inst.src2]);
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break;
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}
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out.Write(inst);
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break;
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}
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}
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}
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return logBlocks;
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}
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