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Henrik RydgårdandClaude Opus 5.5
9d55b8046c
The audio hardware at 0xBE000000, as POPS's ME loop (popsman.prx +2F88) drives it: after setting it up, it writes one stereo sample (left in the low half) to 0x70 whenever status 0x28 bit 5 says the FIFO has room, and sleeps in halt in between on the ME's interrupt source 12. Measured from the ME on a PSP-1000 (pspautotest me/audiofifo): the FIFO holds 24 samples and plays them at 44.1kHz while 0x04 bit 1 is set; status 0x28 has bit 4 while playing, bit 5 while there's room, and bit 1 once it has played out its last sample, a sample after the FIFO empties; and source 12 is a level, up while there's room, which halt wakes on with interrupts disabled. What it plays is mixed into the output. A halted ME used to sleep until the main CPU's next slice. It now wakes within the slice when the full FIFO next has room, as POPS's loop sleeps for every sample. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>