Unknown W. Brackets a181f6d5b8 riscv: Add a comment for FMUL testing later.

2023-07-27 22:16:29 -07:00

..

RiscVAsm.cpp

riscv: Handle rounding mode and ctrl transfers.

2023-07-25 20:33:56 -07:00

RiscVCompALU.cpp

riscv: Implement multiply instructions.

2023-07-23 18:01:50 -07:00

RiscVCompBranch.cpp

riscv: Handle rounding mode and ctrl transfers.

2023-07-25 20:33:56 -07:00

RiscVCompFPU.cpp

riscv: Add a comment for FMUL testing later.

2023-07-27 22:16:29 -07:00

RiscVCompLoadStore.cpp

riscv: Implement simple vec4 ops via floats.

2023-07-25 20:33:56 -07:00

RiscVCompSystem.cpp

riscv: Implement vec4 shuffle and init.

2023-07-25 20:33:56 -07:00

RiscVCompVec.cpp

riscv: Implement vec4 dot.

2023-07-25 20:33:56 -07:00

RiscVJit.cpp

riscv: Cleanup unnecessary fcr31 func.

2023-07-25 20:33:56 -07:00

RiscVJit.h

riscv: Cleanup unnecessary fcr31 func.

2023-07-25 20:33:56 -07:00

RiscVRegCache.cpp

riscv: Add FPU regcache.

2023-07-25 20:33:56 -07:00

RiscVRegCache.h

riscv: Add FPU regcache.

2023-07-25 20:33:56 -07:00

RiscVRegCacheFPU.cpp

riscv: Implement simple vec4 ops via floats.

2023-07-25 20:33:56 -07:00

RiscVRegCacheFPU.h

riscv: Implement simple vec4 ops via floats.

2023-07-25 20:33:56 -07:00