Henrik Rydgård e9431d0d1e Merge pull request #17859 from unknownbrackets/irjit-vec4 ...

irjit: Use Vec4 a bit more

2023-08-06 23:05:33 +02:00

..

IRAnalysis.cpp

Buildfix for VS2017

2023-08-06 15:06:54 +03:00

IRAnalysis.h

riscv: Spill registers more intelligently.

2023-07-30 14:24:12 -07:00

IRAsm.cpp

Remove most instances of base/logging.h from Common, Core, GPU, more

2020-08-15 19:08:44 +02:00

IRCompALU.cpp

irjit: Fix unordered float compares.

2022-10-30 21:12:59 -07:00

IRCompBranch.cpp

riscv: Reduce bloat in jit fallbacks.

2023-07-25 19:42:04 -07:00

IRCompFPU.cpp

irjit: Allow masked vneg.q.

2023-08-06 13:38:00 -07:00

IRCompLoadStore.cpp

irjit: Implement ll/sc.

2023-07-29 17:57:44 -07:00

IRCompVFPU.cpp

Merge pull request #17859 from unknownbrackets/irjit-vec4

2023-08-06 23:05:33 +02:00

IRFrontend.cpp

Core: Cleanup disasm buffer usage.

2023-04-29 09:07:25 -07:00

IRFrontend.h

irjit: Allow Vec4 to be used with masks.

2023-08-06 13:46:24 -07:00

IRInst.cpp

irjit: Implement vqmul, add Vec4Blend.

2023-08-06 13:38:00 -07:00

IRInst.h

irjit: Implement vqmul, add Vec4Blend.

2023-08-06 13:38:00 -07:00

IRInterpreter.cpp

irjit: Implement vqmul, add Vec4Blend.

2023-08-06 13:38:00 -07:00

IRInterpreter.h

jit: Avoid using mips identifier directly.

2021-02-26 07:24:58 -08:00

IRJit.cpp

riscv: Spill registers more intelligently.

2023-07-30 14:24:12 -07:00

IRJit.h

irjit: Move more to IRNativeBackend, split.

2023-08-06 00:16:43 -07:00

IRNativeCommon.cpp

irjit: Implement vqmul, add Vec4Blend.

2023-08-06 13:38:00 -07:00

IRNativeCommon.h

irjit: Move more to IRNativeBackend, split.

2023-08-06 00:16:43 -07:00

IRPassSimplify.cpp

Merge pull request #17859 from unknownbrackets/irjit-vec4

2023-08-06 23:05:33 +02:00

IRPassSimplify.h

irjit: Add constructs for validing mem access.

2022-08-21 13:01:23 -07:00

IRRegCache.cpp

irjit: Consistently dirty vfpuctrl in IR.

2023-08-06 08:36:19 -07:00

IRRegCache.h

irjit: Define a specific IRReg type.

2023-07-23 18:01:00 -07:00