Henrik Rydgård 518795e35f Cut down on outdated/useless REPORTing and logging

2026-10-25 17:33:44 +01:00

..

RiscVAsm.cpp

CPU: Give each MIPSState an address space for its memory accesses

2026-10-20 18:41:28 +02:00

RiscVCompALU.cpp

RISC-V JIT: Compile the bit ops and min/max without Zbb

2026-09-24 14:31:22 -06:00

RiscVCompBranch.cpp

CPU: Give each MIPSState an address space for its memory accesses

2026-10-20 18:41:28 +02:00

RiscVCompFPU.cpp

VFPU: vmin and vmax order zeros and denormals as equal, on every core

2026-10-14 11:59:35 +02:00

RiscVCompLoadStore.cpp

IR native backends: Fix ll into $zero, and sc losing its result

2026-10-14 00:10:00 +02:00

RiscVCompSystem.cpp

HLE: Pass the MIPSState to syscalls and their implementations

2026-10-20 15:45:14 +02:00

RiscVCompVec.cpp

VFPU: Drop the inaccurate dot product paths

2026-10-18 12:11:46 +02:00

RiscVJit.cpp

IR JITs: Split the IR interpreter out, and keep IR to it

2026-10-20 12:09:16 +02:00

RiscVJit.h

IR JITs: Split the IR interpreter out, and keep IR to it

2026-10-20 12:09:16 +02:00

RiscVRegCache.cpp

Cut down on outdated/useless REPORTing and logging

2026-10-25 17:33:44 +01:00

RiscVRegCache.h

RISC-V IR JIT: Run Vec4VfpuDot through a shared routine

2026-10-15 14:42:00 +02:00

RiscVVfpuDot.h

RISC-V IR JIT: Run Vec4VfpuDot through a shared routine

2026-10-15 14:42:00 +02:00