mirror of
https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
307ed26927
A PL080-like controller: channels 4-7 at 0xBC800180, run at once when enabled, following linked list items of five words (source, destination, next, control, configuration). Addresses are physical, and on the ME's bus (a master bit in the control word) the low ones are its eDRAM. Transfer size is in units of the source width. A finished channel with its interrupt bit set shows in 0x04, cleared through 0x08. 0xBC800100-0x10C set the LCD's framebuffer, which goes to sceDisplay. Pixel format 0 is 8888 (mcidclan's samples); others are logged. The colour space conversion registers (0x120-0x160) are only kept so far. Like the other ME devices, this answers only while the ME is emulated. mcidclan's dmacplus-me2sc and sc2me-then-me2sc samples show their transferred eDRAM. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
107 lines
3.9 KiB
C++
107 lines
3.9 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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// The Media Engine, the PSP's second Allegrex. The firmware runs its codecs on it, and homebrew
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// whatever it likes. It runs in its own address space (Memory::CreateMESpace()), on the
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// interpreter, a slice behind the main CPU: CoreTiming runs it for the cycles the main CPU has just
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// used. Only emulated for homebrew, when enabled; commercial games get the HLE codecs.
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#pragma once
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#include <unordered_map>
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#include "Common/CommonTypes.h"
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#include "Core/MIPS/MIPS.h"
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class PointerWrap;
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namespace MeCore {
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// The ME's interrupt controller's source for the main CPU's soft interrupt (0xBC100044).
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enum : u32 {
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ME_INTR_SOFT = 0x80000000,
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};
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struct MEState {
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MIPSState cpu;
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// Held in reset until the main CPU releases it.
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bool inReset = true;
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// Stopped by halt, until an interrupt it doesn't mask is raised.
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bool halted = false;
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// The ME's clock is tickBase - cpu.downcount.
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s64 tickBase = 0;
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// mfic/mtic's interrupt enable, which is per CPU.
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u32 interruptEnable = 0;
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// Its interrupt controller (0xBC300000): raised sources, and the ones that reach the CPU (IP2).
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u32 intcRaised = 0;
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u32 intcEnabled = 0;
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// System registers (0xBC100000): those the ME code we run uses.
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u32 resetFlags = 0; // 0x4C. Bit 2 holds the ME in reset.
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u32 busClock = 0; // 0x50
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u32 nmiFlags = 0; // 0x04
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u32 ramConfig = 0; // 0x40. Bits 0-1: RAM size, 16 << n MB.
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u32 mutex = 0; // 0x48. Bit 0 is the main CPU's, bit 1 the ME's.
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u32 memProtect[20]{}; // 0xBC000000-0xBC00004C
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// DMACplus (0xBC800000), which moves data between the CPUs' memories, and drives the LCD and the
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// colour space conversion. Only what homebrew's ME code uses.
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struct Dmacplus {
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u32 intTCStatus = 0; // 0x04, channels that finished with their interrupt bit set
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u32 lcd[4]{}; // 0x100: framebuffer, pixel format, width, stride
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u32 csc[0x11]{}; // 0x120-0x160: colour space conversion
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u32 channels[4][5]{}; // 0x180-0x1FF: source, destination, next LLI, control, configuration
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} dmacplus;
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// Not saved: whether the code at an address is a wait loop (see IsWaitLoop), and where it ends.
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// 0 for not one. Cleared when the ME's code changes.
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std::unordered_map<u32, u32> waitLoopEnds;
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// Waiting for the main CPU, for the rest of this RunFor.
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bool waiting = false;
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};
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// Null when the ME isn't emulated.
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extern MEState *g_meState;
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// Whether the config and this boot (homebrew) want the ME.
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bool Wanted(bool homebrew);
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// Creates the ME, in reset. Fails on platforms without an ME address space.
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bool Init();
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void Shutdown();
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// Creates or removes the ME to match the state.
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void DoState(PointerWrap &p);
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// Runs the ME for the cycles the main CPU has just run.
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void RunFor(int cycles);
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// Asserting reset stops the ME. Releasing it starts the ME at the reset vector.
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void SetReset(bool asserted);
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// The ME's clock.
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u64 GetTicks();
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// COP0 registers with behaviour on the ME: Compare (11), Cause (13).
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u32 ReadCop0(int reg);
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void WriteCop0(int reg, u32 value);
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void Halt();
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// Raises sources in the ME's interrupt controller.
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void RaiseInterrupt(u32 sources);
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// The ME interrupts the main CPU (it wrote 0xBC100044).
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void InterruptMainCPU();
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} // namespace MeCore
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