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https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
99335adb40
The COP0 register file was a static array in the interpreter, shared by anything that ran kernel code and lost on a savestate load. It's now part of MIPSState and saved with it (MIPSState section version 5). eret returns to EPC, or to ErrorEPC with Status.ERL set, as MIPS32 defines it; that isn't checked against a PSP yet. It and halt carry a new ENDS_BLOCK flag: the IR frontend ends the block after them and exits to whatever PC the interpreter left, and the interpreter's IR-matching block timing stops there too. TestCPUEret runs it on the interpreter, IR interpreter and JIT. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
58 lines
2.3 KiB
C++
58 lines
2.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Common/CommonTypes.h"
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#include "Core/MIPS/MIPS.h"
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int MIPS_InterpretSingleStep(MIPSState *mips);
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namespace MIPSInt
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{
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void Int_Syscall(MIPSState *mips, MIPSOpcode op);
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void Int_mxc1(MIPSState *mips, MIPSOpcode op);
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void Int_Cop0(MIPSState *mips, MIPSOpcode op);
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void Int_Eret(MIPSState *mips, MIPSOpcode op);
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void Int_RelBranch(MIPSState *mips, MIPSOpcode op);
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void Int_RelBranchRI(MIPSState *mips, MIPSOpcode op);
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void Int_IType(MIPSState *mips, MIPSOpcode op);
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void Int_ITypeMem(MIPSState *mips, MIPSOpcode op);
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void Int_RType2(MIPSState *mips, MIPSOpcode op);
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void Int_RType3(MIPSState *mips, MIPSOpcode op);
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void Int_ShiftType(MIPSState *mips, MIPSOpcode op);
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void Int_MulDivType(MIPSState *mips, MIPSOpcode op);
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void Int_JumpType(MIPSState *mips, MIPSOpcode op);
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void Int_JumpRegType(MIPSState *mips, MIPSOpcode op);
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void Int_Allegrex2(MIPSState *mips, MIPSOpcode op);
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void Int_FPULS(MIPSState *mips, MIPSOpcode op);
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void Int_FPU3op(MIPSState *mips, MIPSOpcode op);
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void Int_FPU2op(MIPSState *mips, MIPSOpcode op);
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void Int_Allegrex(MIPSState *mips, MIPSOpcode op);
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void Int_FPUComp(MIPSState *mips, MIPSOpcode op);
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void Int_FPUBranch(MIPSState *mips, MIPSOpcode op);
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void Int_CallReplacement(MIPSState *mips, MIPSOpcode op);
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void Int_Special2(MIPSState *mips, MIPSOpcode op);
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void Int_Special3(MIPSState *mips, MIPSOpcode op);
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void Int_Interrupt(MIPSState *mips, MIPSOpcode op);
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void Int_Cache(MIPSState *mips, MIPSOpcode op);
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void Int_Sync(MIPSState *mips, MIPSOpcode op);
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void Int_Break(MIPSState *mips, MIPSOpcode op);
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void Int_StoreSync(MIPSState *mips, MIPSOpcode op);
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}
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