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https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
b7b4a265b7
The interpreter's MMIO dispatch was a hardcoded chain for GPIO and the syscon serial port. Devices now register an address range in Core/HW/MMIO and get each access with its width and the MIPSState making it, for registers that answer each CPU differently. An access no device handles is logged and reads as poison, as before. GPIO and syscon serial become the first two devices. They're reset at boot, which they never were, and saved in savestates (SaveStart section version 4). ll/sc, lwl/lwr and lwc1/swc1 reach MMIO in the interpreter too, and kernel blocks leave lwc1/swc1 to it like the other loads and stores. swl/swr and lv/sv still treat it as a bad address. TestMMIO runs a kernel-mode access on each core and the registers through a savestate. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
246 lines
6.2 KiB
C++
246 lines
6.2 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/IR/IRFrontend.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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#include "Common/CPUDetect.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// FPCR interesting bits:
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// 24: FZ (flush-to-zero)
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// 23:22: RMode (0 = nearest, 1 = +inf, 2 = -inf, 3 = zero)
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// not much else is interesting for us, but should be preserved.
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// To access: MRS Xt, FPCR ; MSR FPCR, Xt
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE(flag) { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE(flag) if (opts.disableFlags & (uint32_t)JitDisable::flag) { Comp_Generic(op); return; }
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#define DISABLE { Comp_Generic(op); return; }
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#define INVALIDOP { Comp_Generic(op); return; }
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namespace MIPSComp {
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void IRFrontend::Comp_FPU3op(MIPSOpcode op) {
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CONDITIONAL_DISABLE(FPU);
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int ft = _FT;
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int fs = _FS;
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int fd = _FD;
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switch (op & 0x3f) {
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case 0: ir.Write(IROp::FAdd, fd, fs, ft); break; //F(fd) = F(fs) + F(ft); //add
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case 1: ir.Write(IROp::FSub, fd, fs, ft); break; //F(fd) = F(fs) - F(ft); //sub
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case 2: ir.Write(IROp::FMul, fd, fs, ft); break; //F(fd) = F(fs) * F(ft); //mul
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case 3: ir.Write(IROp::FDiv, fd, fs, ft); break; //F(fd) = F(fs) / F(ft); //div
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default:
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INVALIDOP;
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return;
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}
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}
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void IRFrontend::Comp_FPULS(MIPSOpcode op) {
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CONDITIONAL_DISABLE(LSU_FPU);
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s32 offset = _IMM16;
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int ft = _FT;
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MIPSGPReg rs = _RS;
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CheckMemoryBreakpoint(rs, offset);
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if (js.kernelMode) {
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// Kernel code may reach hardware registers (MMIO), which only the interpreter handles.
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DISABLE;
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return;
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}
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switch (op >> 26) {
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case 49: // lwc1
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ir.Write(IROp::LoadFloat, ft, rs, 0, offset);
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break;
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case 57: // swc1
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ir.Write(IROp::StoreFloat, ft, rs, 0, offset);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
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CONDITIONAL_DISABLE(FPU_COMP);
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int opc = op & 0xF;
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if (opc >= 8) opc -= 8; // alias
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if (opc == 0) { // f, sf (signalling false)
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ir.Write(IROp::FpCondFromReg, 0, MIPS_REG_ZERO);
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return;
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}
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int fs = _FS;
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int ft = _FT;
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IRFpCompareMode mode;
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switch (opc) {
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case 1: // un, ngle (unordered)
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mode = IRFpCompareMode::EitherUnordered;
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break;
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case 2: // eq, seq (equal, ordered)
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mode = IRFpCompareMode::EqualOrdered;
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break;
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case 3: // ueq, ngl (equal, unordered)
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mode = IRFpCompareMode::EqualUnordered;
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break;
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case 4: // olt, lt (less than, ordered)
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mode = IRFpCompareMode::LessOrdered;
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break;
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case 5: // ult, nge (less than, unordered)
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mode = IRFpCompareMode::LessUnordered;
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break;
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case 6: // ole, le (less equal, ordered)
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mode = IRFpCompareMode::LessEqualOrdered;
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break;
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case 7: // ule, ngt (less equal, unordered)
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mode = IRFpCompareMode::LessEqualUnordered;
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break;
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default:
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INVALIDOP;
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return;
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}
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ir.Write(IROp::FCmp, (int)mode, fs, ft);
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}
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void IRFrontend::Comp_FPU2op(MIPSOpcode op) {
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CONDITIONAL_DISABLE(FPU);
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int fs = _FS;
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int fd = _FD;
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switch (op & 0x3f) {
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case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
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ir.Write(IROp::FSqrt, fd, fs);
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break;
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case 5: //F(fd) = fabsf(F(fs)); break; //abs
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ir.Write(IROp::FAbs, fd, fs);
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break;
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case 6: //F(fd) = F(fs); break; //mov
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if (fd != fs)
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ir.Write(IROp::FMov, fd, fs);
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break;
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case 7: //F(fd) = -F(fs); break; //neg
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ir.Write(IROp::FNeg, fd, fs);
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break;
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case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
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ir.Write(IROp::FRound, fd, fs);
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break;
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case 13: //FsI(fd) = Rto0(F(fs))); break; //trunc.w.s
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ir.Write(IROp::FTrunc, fd, fs);
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break;
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case 14://FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
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ir.Write(IROp::FCeil, fd, fs);
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break;
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case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
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ir.Write(IROp::FFloor, fd, fs);
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break;
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case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
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ir.Write(IROp::FCvtSW, fd, fs);
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break;
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case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
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ir.Write(IROp::FCvtWS, fd, fs);
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break;
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default:
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INVALIDOP;
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}
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}
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void IRFrontend::Comp_mxc1(MIPSOpcode op) {
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CONDITIONAL_DISABLE(FPU_XFER);
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int fs = _FS;
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MIPSGPReg rt = _RT;
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switch ((op >> 21) & 0x1f) {
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case 0: // R(rt) = FI(fs); break; //mfc1
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if (rt == MIPS_REG_ZERO) {
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return;
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}
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ir.Write(IROp::FMovToGPR, rt, fs);
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return;
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case 2: //cfc1
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if (rt == MIPS_REG_ZERO) {
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return;
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}
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if (fs == 31) {
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// This needs to insert fpcond.
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ir.Write(IROp::FpCtrlToReg, rt);
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} else if (fs == 0) {
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ir.WriteSetConstant(rt, MIPSState::FCR0_VALUE);
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} else {
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// Unsupported regs are always 0.
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ir.WriteSetConstant(rt, 0);
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}
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return;
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case 4: //FI(fs) = R(rt); break; //mtc1
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ir.Write(IROp::FMovFromGPR, fs, rt);
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return;
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case 6: //ctc1
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if (fs == 31) {
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// Set rounding mode
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RestoreRoundingMode();
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ir.Write(IROp::FpCtrlFromReg, 0, rt);
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// TODO: Do the UpdateRoundingMode check at runtime?
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UpdateRoundingMode();
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ApplyRoundingMode();
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} else {
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// Maybe not strictly invalid? But likely invalid.
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INVALIDOP;
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}
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return;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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