mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-15 07:20:31 +02:00
Henrik RydgårdandClaude Opus 5.5
ae32477764
With the software renderer, which now stores depth as the GE does, a 16-bit read or write at VRAM's 0x04200000 or 0x04600000 mirror goes to where the GE's 16-bit or 32-bit color layout puts that depth pixel (ppsspp-re geprobe exp88: the mirrors are the layout's exact inverse). Games access depth there with nothing else, so other widths stay plain. The accessors check the address, then whether the GPU core is the software renderer (CoreParameter); the hardware renderers keep depth plain and handle the layout their own way. The renderer keeps the layouts up to date with the EDRAM address translation. With it, the JITs send 16-bit loads and stores to the interpreter, and the IR passes don't change a load's width to or from 16 bits. The pspautotests that read depth through the mirrors now do so 16 bits at a time, re-recorded on hardware unchanged. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
425 lines
13 KiB
C++
425 lines
13 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#include "Core/MemMap.h"
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#include "Core/Config.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/ARM/ArmJit.h"
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#include "Core/MIPS/ARM/ArmRegCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE(flag) { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp
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{
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using namespace ArmGen;
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using namespace ArmJitConstants;
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void ArmJit::SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset) {
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Operand2 op2;
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if (offset) {
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bool negated;
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if (TryMakeOperand2_AllowNegation(offset, op2, &negated)) {
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if (!negated)
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ADD(R0, gpr.R(rs), op2);
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else
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SUB(R0, gpr.R(rs), op2);
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} else {
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// Try to avoid using MOVT
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if (offset < 0) {
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gpr.SetRegImm(R0, (u32)(-offset));
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SUB(R0, gpr.R(rs), R0);
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} else {
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gpr.SetRegImm(R0, (u32)offset);
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ADD(R0, gpr.R(rs), R0);
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}
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}
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BIC(R0, R0, Operand2(0xC0, 4)); // &= 0x3FFFFFFF
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} else {
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BIC(R0, gpr.R(rs), Operand2(0xC0, 4)); // &= 0x3FFFFFFF
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}
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}
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void ArmJit::SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg, bool reverse) {
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SetR0ToEffectiveAddress(rs, offset);
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// There are three valid ranges. Each one gets a bit.
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const u32 BIT_SCRATCH = 1, BIT_RAM = 2, BIT_VRAM = 4;
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MOVI2R(tempReg, BIT_SCRATCH | BIT_RAM | BIT_VRAM);
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CMP(R0, AssumeMakeOperand2(PSP_GetScratchpadMemoryBase()));
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SetCC(CC_LO);
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BIC(tempReg, tempReg, BIT_SCRATCH);
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SetCC(CC_HS);
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CMP(R0, AssumeMakeOperand2(PSP_GetScratchpadMemoryEnd()));
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BIC(tempReg, tempReg, BIT_SCRATCH);
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// If it was in that range, later compares don't matter.
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CMP(R0, AssumeMakeOperand2(PSP_GetVidMemBase()));
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SetCC(CC_LO);
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BIC(tempReg, tempReg, BIT_VRAM);
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SetCC(CC_HS);
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CMP(R0, AssumeMakeOperand2(PSP_GetVidMemEnd()));
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BIC(tempReg, tempReg, BIT_VRAM);
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CMP(R0, AssumeMakeOperand2(PSP_GetKernelMemoryBase()));
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SetCC(CC_LO);
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BIC(tempReg, tempReg, BIT_RAM);
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SetCC(CC_HS);
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CMP(R0, AssumeMakeOperand2(PSP_GetUserMemoryEnd()));
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BIC(tempReg, tempReg, BIT_RAM);
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// If we left any bit set, the address is OK.
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SetCC(CC_AL);
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CMP(tempReg, 0);
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SetCC(reverse ? CC_EQ : CC_GT);
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}
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void ArmJit::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
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CONDITIONAL_DISABLE(LSU);
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CheckMemoryBreakpoint();
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int offset = SignExtend16ToS32(op & 0xFFFF);
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (!js.inDelaySlot && !jo.Disabled(JitDisable::LSU_UNALIGNED)) {
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// Optimisation: Combine to single unaligned load/store
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bool isLeft = (o == 34 || o == 42);
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CheckMemoryBreakpoint(1);
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Find a matching shift in opposite direction with opposite offset.
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if (nextOp == (isLeft ? (op.encoding + (4<<26) - 3)
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: (op.encoding - (4<<26) + 3)))
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{
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EatInstruction(nextOp);
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nextOp = MIPSOpcode(((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF)); //lw, sw
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Comp_ITypeMem(nextOp);
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return;
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}
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}
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u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
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bool doCheck = false;
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FixupBranch skip;
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if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
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u32 addr = iaddr & 0x3FFFFFFF;
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// Need to initialize since this only loads part of the register.
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// But rs no longer matters (even if rs == rt) since we have the address.
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gpr.MapReg(rt, load ? MAP_DIRTY : 0);
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gpr.SetRegImm(R0, addr & ~3);
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u8 shift = (addr & 3) * 8;
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switch (o) {
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case 34: // lwl
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LDR(R0, MEMBASEREG, R0);
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ANDI2R(gpr.R(rt), gpr.R(rt), 0x00ffffff >> shift, SCRATCHREG2);
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, 24 - shift));
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break;
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case 38: // lwr
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LDR(R0, MEMBASEREG, R0);
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ANDI2R(gpr.R(rt), gpr.R(rt), 0xffffff00 << (24 - shift), SCRATCHREG2);
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSR, shift));
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break;
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case 42: // swl
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LDR(SCRATCHREG2, MEMBASEREG, R0);
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// Don't worry, can't use temporary.
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ANDI2R(SCRATCHREG2, SCRATCHREG2, 0xffffff00 << shift, R0);
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ORR(SCRATCHREG2, SCRATCHREG2, Operand2(gpr.R(rt), ST_LSR, 24 - shift));
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STR(SCRATCHREG2, MEMBASEREG, R0);
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break;
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case 46: // swr
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LDR(SCRATCHREG2, MEMBASEREG, R0);
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// Don't worry, can't use temporary.
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ANDI2R(SCRATCHREG2, SCRATCHREG2, 0x00ffffff >> (24 - shift), R0);
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ORR(SCRATCHREG2, SCRATCHREG2, Operand2(gpr.R(rt), ST_LSL, shift));
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STR(SCRATCHREG2, MEMBASEREG, R0);
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break;
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}
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return;
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}
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// This gets hit in a few games, as a result of never-taken delay slots (some branch types
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// conditionally execute the delay slot instructions). Ignore in those cases.
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if (!js.inDelaySlot) {
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_dbg_assert_msg_(!gpr.IsImm(rs), "Invalid immediate address %08x? CPU bug?", iaddr);
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}
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if (load) {
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gpr.MapDirtyIn(rt, rs, false);
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} else {
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gpr.MapInIn(rt, rs);
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}
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if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
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SetCCAndR0ForSafeAddress(rs, offset, SCRATCHREG2, true);
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doCheck = true;
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} else {
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SetR0ToEffectiveAddress(rs, offset);
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}
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if (doCheck) {
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skip = B();
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}
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SetCC(CC_AL);
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// Need temp regs. TODO: Get from the regcache?
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static const ARMReg LR_SCRATCHREG3 = R9;
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static const ARMReg LR_SCRATCHREG4 = R10;
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if (load) {
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PUSH(1, LR_SCRATCHREG3);
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} else {
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PUSH(2, LR_SCRATCHREG3, LR_SCRATCHREG4);
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}
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// Here's our shift amount.
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AND(SCRATCHREG2, R0, 3);
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LSL(SCRATCHREG2, SCRATCHREG2, 3);
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// Now align the address for the actual read.
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BIC(R0, R0, 3);
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switch (o) {
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case 34: // lwl
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MOVI2R(LR_SCRATCHREG3, 0x00ffffff);
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LDR(R0, MEMBASEREG, R0);
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AND(gpr.R(rt), gpr.R(rt), Operand2(LR_SCRATCHREG3, ST_LSR, SCRATCHREG2));
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, SCRATCHREG2));
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break;
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case 38: // lwr
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MOVI2R(LR_SCRATCHREG3, 0xffffff00);
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LDR(R0, MEMBASEREG, R0);
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LSR(R0, R0, SCRATCHREG2);
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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AND(gpr.R(rt), gpr.R(rt), Operand2(LR_SCRATCHREG3, ST_LSL, SCRATCHREG2));
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ORR(gpr.R(rt), gpr.R(rt), R0);
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break;
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case 42: // swl
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MOVI2R(LR_SCRATCHREG3, 0xffffff00);
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LDR(LR_SCRATCHREG4, MEMBASEREG, R0);
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AND(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(LR_SCRATCHREG3, ST_LSL, SCRATCHREG2));
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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ORR(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(gpr.R(rt), ST_LSR, SCRATCHREG2));
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STR(LR_SCRATCHREG4, MEMBASEREG, R0);
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break;
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case 46: // swr
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MOVI2R(LR_SCRATCHREG3, 0x00ffffff);
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LDR(LR_SCRATCHREG4, MEMBASEREG, R0);
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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AND(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(LR_SCRATCHREG3, ST_LSR, SCRATCHREG2));
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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ORR(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(gpr.R(rt), ST_LSL, SCRATCHREG2));
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STR(LR_SCRATCHREG4, MEMBASEREG, R0);
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break;
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}
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if (load) {
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POP(1, LR_SCRATCHREG3);
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} else {
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POP(2, LR_SCRATCHREG3, LR_SCRATCHREG4);
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}
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if (doCheck) {
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SetJumpTarget(skip);
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}
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}
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void ArmJit::Comp_ITypeMem(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE(LSU);
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CheckMemoryBreakpoint();
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if (js.kernelMode) {
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// Send all memory accesses to the interpreter in kernel mode.
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// TODO: Do something faster - but it hardly matters, currently this is VSH-only.
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DISABLE;
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return;
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}
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int offset = (signed short)(op&0xFFFF);
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bool load = false;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op>>26;
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// 16-bit accesses can go through the depth layout (Memory::DepthMirrored16).
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if (Memory::DepthMirrorsActive() && (o == 33 || o == 37 || o == 41)) {
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DISABLE;
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}
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if (((op >> 29) & 1) == 0 && rt == MIPS_REG_ZERO) {
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// Don't load anything into $zr
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return;
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}
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u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
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bool doCheck = false;
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ARMReg addrReg = R0;
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switch (o) {
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case 32: //lb
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case 33: //lh
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case 35: //lw
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case 36: //lbu
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case 37: //lhu
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load = true;
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case 40: //sb
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case 41: //sh
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case 43: //sw
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// Map base register as pointer and go from there - if the displacement isn't too big.
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// This is faster if there are multiple loads from the same pointer. Need to hook up the MIPS analyzer..
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if (jo.cachePointers && g_Config.bFastMemory) {
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// ARM has smaller load/store immediate displacements than MIPS, 12 bits - and some memory ops only have 8 bits.
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int offsetRange = 0x3ff;
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if (o == 41 || o == 33 || o == 37 || o == 32)
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offsetRange = 0xff; // 8 bit offset only
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if (!gpr.IsImm(rs) && rs != rt && (offset <= offsetRange) && offset >= -offsetRange) {
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gpr.SpillLock(rs, rt);
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gpr.MapRegAsPointer(rs);
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gpr.MapReg(rt, load ? MAP_NOINIT : 0);
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switch (o) {
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case 35: LDR (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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case 37: LDRH (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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case 33: LDRSH(gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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case 36: LDRB (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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case 32: LDRSB(gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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// Store
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case 43: STR (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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case 41: STRH (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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case 40: STRB (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
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}
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gpr.ReleaseSpillLocks();
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break;
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}
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}
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if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
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// TODO: Avoid mapping a register for the "zero" register, use R0 instead.
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// We can compute the full address at compile time. Kickass.
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u32 addr = iaddr & 0x3FFFFFFF;
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if (addr == iaddr && offset == 0) {
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// It was already safe. Let's shove it into a reg and use it directly.
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load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
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addrReg = gpr.R(rs);
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} else {
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// In this case, only map rt. rs+offset will be in R0.
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gpr.MapReg(rt, load ? MAP_NOINIT : 0);
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gpr.SetRegImm(R0, addr);
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addrReg = R0;
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}
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} else {
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_dbg_assert_msg_(!gpr.IsImm(rs), "Invalid immediate address? CPU bug?");
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load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
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if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
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SetCCAndR0ForSafeAddress(rs, offset, SCRATCHREG2);
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doCheck = true;
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} else {
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SetR0ToEffectiveAddress(rs, offset);
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}
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addrReg = R0;
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}
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switch (o)
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{
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// Load
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case 35: LDR (gpr.R(rt), MEMBASEREG, addrReg); break;
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case 37: LDRH (gpr.R(rt), MEMBASEREG, addrReg); break;
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case 33: LDRSH(gpr.R(rt), MEMBASEREG, addrReg); break;
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case 36: LDRB (gpr.R(rt), MEMBASEREG, addrReg); break;
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case 32: LDRSB(gpr.R(rt), MEMBASEREG, addrReg); break;
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// Store
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case 43: STR (gpr.R(rt), MEMBASEREG, addrReg); break;
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case 41: STRH (gpr.R(rt), MEMBASEREG, addrReg); break;
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case 40: STRB (gpr.R(rt), MEMBASEREG, addrReg); break;
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}
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if (doCheck) {
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if (load) {
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SetCC(CC_EQ);
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MOVI2R(gpr.R(rt), 0);
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}
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SetCC(CC_AL);
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}
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break;
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case 34: //lwl
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case 38: //lwr
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load = true;
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case 42: //swl
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case 46: //swr
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Comp_ITypeMemLR(op, load);
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break;
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default:
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Comp_Generic(op);
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return;
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}
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}
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void ArmJit::Comp_StoreSync(MIPSOpcode op) {
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CONDITIONAL_DISABLE(LSU);
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DISABLE;
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}
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void ArmJit::Comp_Cache(MIPSOpcode op) {
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CONDITIONAL_DISABLE(LSU);
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int func = (op >> 16) & 0x1F;
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// See Int_Cache for the definitions.
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switch (func) {
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case 24: break;
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case 25: break;
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case 27: break;
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case 30: break;
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default:
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// Fall back to the interpreter.
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DISABLE;
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}
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}
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}
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#endif // PPSSPP_ARCH(ARM)
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