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ppsspp/Core/MIPS/IR
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Unknown W. Brackets b03398a46c Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
..
IRAnalysis.cpp
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
IRAnalysis.h
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
IRAsm.cpp
Remove most instances of base/logging.h from Common, Core, GPU, more
2020-08-15 19:08:44 +02:00
IRCompALU.cpp
irjit: Fix unordered float compares.
2022-10-30 21:12:59 -07:00
IRCompBranch.cpp
riscv: Reduce bloat in jit fallbacks.
2023-07-25 19:42:04 -07:00
IRCompFPU.cpp
irjit: Cleanup self-fmovs.
2023-07-30 14:16:17 -07:00
IRCompLoadStore.cpp
irjit: Implement ll/sc.
2023-07-29 17:57:44 -07:00
IRCompVFPU.cpp
irjit: Cleanup self-fmovs.
2023-07-30 14:16:17 -07:00
IRFrontend.cpp
Core: Cleanup disasm buffer usage.
2023-04-29 09:07:25 -07:00
IRFrontend.h
irjit: Implement ll/sc.
2023-07-29 17:57:44 -07:00
IRInst.cpp
Merge pull request #17815 from unknownbrackets/riscv-jit
2023-07-30 14:49:37 -07:00
IRInst.h
riscv: Implement ll/sc.
2023-07-30 00:45:51 -07:00
IRInterpreter.cpp
Merge pull request #17801 from unknownbrackets/irjit-vminmax
2023-07-30 09:18:25 +02:00
IRInterpreter.h
jit: Avoid using mips identifier directly.
2021-02-26 07:24:58 -08:00
IRJit.cpp
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
IRJit.h
riscv: Use jit address offsets directly.
2023-07-29 19:02:15 -07:00
IRPassSimplify.cpp
Merge pull request #17815 from unknownbrackets/riscv-jit
2023-07-30 14:49:37 -07:00
IRPassSimplify.h
irjit: Add constructs for validing mem access.
2022-08-21 13:01:23 -07:00
IRRegCache.cpp
irjit: Define a specific IRReg type.
2023-07-23 18:01:00 -07:00
IRRegCache.h
irjit: Define a specific IRReg type.
2023-07-23 18:01:00 -07:00