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Unknown W. Brackets
ab809bd19e
Otherwise, the block will be executed with the wrong rounding mode the first time rounding is set. This could be important if it was set for a single operation. This is only a problem the first time it's set.
322 lines
10 KiB
C++
322 lines
10 KiB
C++
// Copyright (c) 2015- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM64)
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#include "base/logging.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/System.h"
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#include "Core/CoreTiming.h"
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#include "Common/MemoryUtil.h"
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#include "Common/CPUDetect.h"
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#include "Common/Arm64Emitter.h"
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#include "Core/MIPS/ARM64/Arm64Jit.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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using namespace Arm64Gen;
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//static int temp32; // unused?
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static const bool enableDebug = false;
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static const bool enableDisasm = false;
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//static bool enableStatistics = false; //unused?
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// ARM64 calling conventions
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// Standard: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf
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// Apple: https://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/Articles/ARM64FunctionCallingConventions.html
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// Summary:
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// ===========
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// SP ("x31") is not a GPR so irrelevant.
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// x0-x7: 8 parameter/result registers
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// x8: "Indirect result location register" (points to struct return values? I think we can map this)
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// x9-x15: 7 temporary registers (no need to save)
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// x16: temporary register/procedure call scratch register 1
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// x17: temporary register/procedure call scratch register 2
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// x18: unavailable (reserved for use by the OS or linker or whatever - iOS, for example, uses it)
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// x19-x28: 10 callee-saved registers
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// x29: the frame pointer register
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// x30: link register for procedure calls
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// So: Scratch registers: x16, x17
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// Mappable registers in priority order:
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// x19, x20, x21, x22, x23, (x24, x25, x26, x27, x28), x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x0, x1,
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// That's a whole lot of registers so we might be able to statically allocate a bunch of common MIPS registers.
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// We should put statically allocated registers in the 7 callee-save regs that are left over after the system regs (x19-x25), so we don't have to bother with
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// saving them when we call out of the JIT. We will perform regular dynamic register allocation in the rest (x0-x15)
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// STATIC ALLOCATION ARM64 (these are all callee-save registers):
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// x23 : Down counter
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// x24 : PC save on JR with non-nice delay slot (to be eliminated later?)
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// x25 : MSR/MRS temporary (to be eliminated later)
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// x26 : JIT base reg
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// x27 : MIPS state (Could eliminate by placing the MIPS state right at the memory base)
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// x28 : Memory base pointer.
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extern volatile CoreState coreState;
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void ShowPC(u32 downcount, void *membase, void *jitbase) {
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static int count = 0;
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if (currentMIPS) {
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ELOG("ShowPC : %08x Downcount : %08x %d %p %p", currentMIPS->pc, downcount, count, membase, jitbase);
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} else {
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ELOG("Universe corrupt?");
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}
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//if (count > 2000)
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// exit(0);
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count++;
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}
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void DisassembleArm(const u8 *data, int size);
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// PLAN: no more block numbers - crazy opcodes just contain offset within
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// dynarec buffer
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// At this offset - 4, there is an int specifying the block number.
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namespace MIPSComp {
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using namespace Arm64JitConstants;
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void Arm64Jit::GenerateFixedCode(const JitOptions &jo) {
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const u8 *start = AlignCodePage();
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BeginWrite();
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if (jo.useStaticAlloc) {
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saveStaticRegisters = AlignCode16();
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STR(INDEX_UNSIGNED, DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
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gpr.EmitSaveStaticRegisters();
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RET();
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loadStaticRegisters = AlignCode16();
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gpr.EmitLoadStaticRegisters();
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LDR(INDEX_UNSIGNED, DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
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RET();
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start = saveStaticRegisters;
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} else {
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saveStaticRegisters = nullptr;
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loadStaticRegisters = nullptr;
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}
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restoreRoundingMode = AlignCode16(); {
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MRS(SCRATCH2_64, FIELD_FPCR);
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// We are not in flush-to-zero mode outside the JIT, so let's turn it off.
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uint32_t mask = ~(4 << 22);
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// Assume we're always in round-to-nearest mode beforehand.
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mask &= ~(3 << 22);
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ANDI2R(SCRATCH2, SCRATCH2, mask);
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_MSR(FIELD_FPCR, SCRATCH2_64);
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RET();
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}
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applyRoundingMode = AlignCode16(); {
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LDR(INDEX_UNSIGNED, SCRATCH2, CTXREG, offsetof(MIPSState, fcr31));
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TSTI2R(SCRATCH2, 1 << 24);
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ANDI2R(SCRATCH2, SCRATCH2, 3);
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FixupBranch skip1 = B(CC_EQ);
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ADDI2R(SCRATCH2, SCRATCH2, 4);
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SetJumpTarget(skip1);
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// We can skip if the rounding mode is nearest (0) and flush is not set.
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// (as restoreRoundingMode cleared it out anyway)
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CMPI2R(SCRATCH2, 0);
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FixupBranch skip = B(CC_EQ);
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// MIPS Rounding Mode: ARM Rounding Mode
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// 0: Round nearest 0
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// 1: Round to zero 3
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// 2: Round up (ceil) 1
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// 3: Round down (floor) 2
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ANDI2R(SCRATCH1, SCRATCH2, 3);
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CMPI2R(SCRATCH1, 1);
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FixupBranch skipadd = B(CC_NEQ);
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ADDI2R(SCRATCH2, SCRATCH2, 2);
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SetJumpTarget(skipadd);
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FixupBranch skipsub = B(CC_LE);
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SUBI2R(SCRATCH2, SCRATCH2, 1);
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SetJumpTarget(skipsub);
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// Actually change the system FPCR register
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MRS(SCRATCH1_64, FIELD_FPCR);
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// Clear both flush-to-zero and rounding before re-setting them.
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ANDI2R(SCRATCH1, SCRATCH1, ~((4 | 3) << 22));
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ORR(SCRATCH1, SCRATCH1, SCRATCH2, ArithOption(SCRATCH2, ST_LSL, 22));
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_MSR(FIELD_FPCR, SCRATCH1_64);
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SetJumpTarget(skip);
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RET();
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}
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updateRoundingMode = AlignCode16(); {
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LDR(INDEX_UNSIGNED, SCRATCH2, CTXREG, offsetof(MIPSState, fcr31));
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// Set SCRATCH2 to FZ:RM (FZ is bit 24, and RM are lowest 2 bits.)
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TSTI2R(SCRATCH2, 1 << 24);
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ANDI2R(SCRATCH2, SCRATCH2, 3);
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FixupBranch skip = B(CC_EQ);
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ADDI2R(SCRATCH2, SCRATCH2, 4);
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SetJumpTarget(skip);
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// Let's update js.currentRoundingFunc with the right convertS0ToSCRATCH1 func.
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MOVP2R(SCRATCH1_64, convertS0ToSCRATCH1);
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LSL(SCRATCH2, SCRATCH2, 3);
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LDR(SCRATCH2_64, SCRATCH1_64, SCRATCH2);
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MOVP2R(SCRATCH1_64, &js.currentRoundingFunc);
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STR(INDEX_UNSIGNED, SCRATCH2_64, SCRATCH1_64, 0);
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RET();
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}
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enterDispatcher = AlignCode16();
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uint32_t regs_to_save = Arm64Gen::ALL_CALLEE_SAVED;
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uint32_t regs_to_save_fp = Arm64Gen::ALL_CALLEE_SAVED_FP;
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fp.ABI_PushRegisters(regs_to_save, regs_to_save_fp);
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// Fixed registers, these are always kept when in Jit context.
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MOVP2R(MEMBASEREG, Memory::base);
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MOVP2R(CTXREG, mips_);
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MOVP2R(JITBASEREG, GetBasePtr());
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LoadStaticRegisters();
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MovFromPC(SCRATCH1);
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outerLoopPCInSCRATCH1 = GetCodePtr();
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MovToPC(SCRATCH1);
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outerLoop = GetCodePtr();
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SaveStaticRegisters(); // Advance can change the downcount, so must save/restore
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RestoreRoundingMode(true);
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QuickCallFunction(SCRATCH1_64, &CoreTiming::Advance);
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ApplyRoundingMode(true);
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LoadStaticRegisters();
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FixupBranch skipToCoreStateCheck = B(); //skip the downcount check
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dispatcherCheckCoreState = GetCodePtr();
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// The result of slice decrementation should be in flags if somebody jumped here
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// IMPORTANT - We jump on negative, not carry!!!
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FixupBranch bailCoreState = B(CC_MI);
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SetJumpTarget(skipToCoreStateCheck);
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MOVP2R(SCRATCH1_64, &coreState);
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LDR(INDEX_UNSIGNED, SCRATCH1, SCRATCH1_64, 0);
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CMP(SCRATCH1, 0);
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FixupBranch badCoreState = B(CC_NEQ);
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FixupBranch skipToRealDispatch2 = B(); //skip the sync and compare first time
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dispatcherPCInSCRATCH1 = GetCodePtr();
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// TODO: Do we always need to write PC to RAM here?
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MovToPC(SCRATCH1);
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// At this point : flags = EQ. Fine for the next check, no need to jump over it.
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dispatcher = GetCodePtr();
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// The result of slice decrementation should be in flags if somebody jumped here
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// IMPORTANT - We jump on negative, not carry!!!
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FixupBranch bail = B(CC_MI);
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SetJumpTarget(skipToRealDispatch2);
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dispatcherNoCheck = GetCodePtr();
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// Debug
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if (enableDebug) {
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MOV(W0, DOWNCOUNTREG);
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MOV(X1, MEMBASEREG);
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MOV(X2, JITBASEREG);
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QuickCallFunction(SCRATCH1_64, (void *)&ShowPC);
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}
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LDR(INDEX_UNSIGNED, SCRATCH1, CTXREG, offsetof(MIPSState, pc));
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LDR(SCRATCH1, MEMBASEREG, SCRATCH1_64);
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LSR(SCRATCH2, SCRATCH1, 24); // or UBFX(SCRATCH2, SCRATCH1, 24, 8)
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ANDI2R(SCRATCH1, SCRATCH1, 0x00FFFFFF);
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CMP(SCRATCH2, MIPS_EMUHACK_OPCODE >> 24);
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FixupBranch skipJump = B(CC_NEQ);
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ADD(SCRATCH1_64, JITBASEREG, SCRATCH1_64);
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BR(SCRATCH1_64);
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SetJumpTarget(skipJump);
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// No block found, let's jit. I don't think we actually need to save static regs that are in callee-save regs here but whatever.
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// Also, rounding mode gotta be irrelevant here..
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SaveStaticRegisters();
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RestoreRoundingMode(true);
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QuickCallFunction(SCRATCH1_64, (void *)&MIPSComp::JitAt);
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ApplyRoundingMode(true);
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LoadStaticRegisters();
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B(dispatcherNoCheck); // no point in special casing this
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SetJumpTarget(bail);
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SetJumpTarget(bailCoreState);
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MOVP2R(SCRATCH1_64, &coreState);
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LDR(INDEX_UNSIGNED, SCRATCH1, SCRATCH1_64, 0);
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CMP(SCRATCH1, 0);
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B(CC_EQ, outerLoop);
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SetJumpTarget(badCoreState);
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breakpointBailout = GetCodePtr();
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SaveStaticRegisters();
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RestoreRoundingMode(true);
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fp.ABI_PopRegisters(regs_to_save, regs_to_save_fp);
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RET();
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// Generate some integer conversion funcs.
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// MIPS order!
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static const RoundingMode roundModes[8] = { ROUND_N, ROUND_Z, ROUND_P, ROUND_M, ROUND_N, ROUND_Z, ROUND_P, ROUND_M };
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for (size_t i = 0; i < ARRAY_SIZE(roundModes); ++i) {
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convertS0ToSCRATCH1[i] = AlignCode16();
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fp.FCMP(S0, S0); // Detect NaN
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fp.FCVTS(S0, S0, roundModes[i]);
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FixupBranch skip = B(CC_VC);
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MOVI2R(SCRATCH2, 0x7FFFFFFF);
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fp.FMOV(S0, SCRATCH2);
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SetJumpTarget(skip);
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RET();
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}
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// Leave this at the end, add more stuff above.
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if (enableDisasm) {
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std::vector<std::string> lines = DisassembleArm64(start, GetCodePtr() - start);
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for (auto s : lines) {
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INFO_LOG(JIT, "%s", s.c_str());
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}
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}
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// Let's spare the pre-generated code from unprotect-reprotect.
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AlignCodePage();
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jitStartOffset = (int)(GetCodePtr() - start);
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// Don't forget to zap the instruction cache! This must stay at the end of this function.
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FlushIcache();
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EndWrite();
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}
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} // namespace MIPSComp
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#endif // PPSSPP_ARCH(ARM64)
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