Henrik RydgårdandClaude Opus 5.5 6fc4eb19df VFPU: Fix vrot with the angle in a destination lane ...

The cosine is then taken of what vrot wrote to that lane: the sine, or zero.
The IR looked at the sine lane instead of the lane holding the angle, and the
legacy JITs ignored the overlap. The assembler refuses such a vrot, so those
now leave it to the interpreter, and don't pair one with the vrot before it.

Covered by the new cpu/vfpu/vrot test.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-09-24 16:22:41 -06:00

..

ArmAsm.cpp

Add a MIPSState context pointer to the JitAt call

2026-09-21 17:34:10 -06:00

ArmCompALU.cpp

MIPS: INT_MIN / -1 leaves HI at zero, like the hardware

2026-09-22 11:02:20 -06:00

ArmCompBranch.cpp

Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.

2026-08-15 19:14:13 +02:00

ArmCompFPU.cpp

Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses)

2026-08-25 00:22:40 +02:00

ArmCompLoadStore.cpp

Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses)

2026-08-25 00:22:40 +02:00

ArmCompReplace.cpp

cmake: Detect features at compile time

2016-10-19 12:31:19 +02:00

ArmCompVFPU.cpp

VFPU: Fix vrot with the angle in a destination lane

2026-09-24 16:22:41 -06:00

ArmJit.cpp

Move the temporary breakpoint out of the user's breakpoint list

2026-08-17 00:29:26 +02:00

ArmJit.h

VFPU: vsqrt, vrsq, vrcp and vnrcp are exact in every backend

2026-09-24 12:24:42 -06:00

ArmRegCache.cpp

Remove more vestiges of old experiments

2026-02-12 01:23:48 +01:00

ArmRegCache.h

Remove more vestiges of old experiments

2026-02-12 01:23:48 +01:00

ArmRegCacheFPU.cpp

mips/regcache: fix before check index after access data array by index

2026-04-28 10:55:55 +02:00

ArmRegCacheFPU.h

VFPU: vsqrt, vrsq, vrcp and vnrcp are exact in every backend

2026-09-24 12:24:42 -06:00