mirror of
https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
6d105ae35d
The backend follows the ARM64 one: a dispatcher, a register cache on top of the IR one, and native exits, syscalls, breakpoints and transfers. Everything else goes to the IR interpreter for now. Floats are mapped one lane per S register (no SIMD mapping yet), and addresses are masked, as on every 32-bit build. The JIT core now uses it on ARM32 in place of the old ArmJit. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
89 lines
2.9 KiB
C++
89 lines
2.9 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#include "Common/ArmEmitter.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/IR/IRJit.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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namespace ArmIRJitConstants {
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const ArmGen::ARMReg DOWNCOUNTREG = ArmGen::R9;
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const ArmGen::ARMReg CTXREG = ArmGen::R10;
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const ArmGen::ARMReg MEMBASEREG = ArmGen::R11;
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const ArmGen::ARMReg SCRATCH1 = ArmGen::R0;
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const ArmGen::ARMReg SCRATCH2 = ArmGen::R1;
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// S0-S3 (Q0) are never allocated.
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const ArmGen::ARMReg SCRATCHF1 = ArmGen::S0;
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const ArmGen::ARMReg SCRATCHF2 = ArmGen::S1;
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const ArmGen::ARMReg SCRATCHF3 = ArmGen::S2;
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const ArmGen::ARMReg SCRATCHF4 = ArmGen::S3;
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} // namespace ArmIRJitConstants
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// Native regs are numbered as ARMReg: R0-R15, then S0-S31. Floats are only mapped as single lanes
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// (mapFPUSIMD is off), so a vector op sees its lanes in separate S regs.
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class ArmIRRegCache : public IRNativeRegCacheBase {
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public:
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ArmIRRegCache(MIPSComp::JitOptions *jo);
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void Init(ArmGen::ARMXEmitter *emitter);
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// May fail and return INVALID_REG if it needs flushing.
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ArmGen::ARMReg TryMapTempImm(IRReg reg);
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// Returns an ARM register containing the requested MIPS register.
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ArmGen::ARMReg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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ArmGen::ARMReg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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ArmGen::ARMReg MapWithFPRTemp(const IRInst &inst);
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void FlushBeforeCall();
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void FlushAll(bool gprs = true, bool fprs = true) override;
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ArmGen::ARMReg GetAndLockTempGPR();
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ArmGen::ARMReg GetAndLockTempFPR();
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ArmGen::ARMReg R(IRReg preg);
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ArmGen::ARMReg F(IRReg preg);
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protected:
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const int *GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const override;
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void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) override;
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bool IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) override;
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void LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void SetNativeRegValue(IRNativeReg nreg, uint32_t imm) override;
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void StoreRegValue(IRReg mreg, uint32_t imm) override;
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private:
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ArmGen::ARMXEmitter *emit_ = nullptr;
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enum {
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NUM_GPRS = 16,
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NUM_FPRS = 32,
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};
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};
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#endif
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