mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-17 08:20:30 +02:00
Henrik RydgårdandClaude Opus 5.5
6a2fa313e6
The cores charged cycles differently and checked downcount at different places, so interrupts and thread switches landed on different instructions, and a game could take a different path on each core. - IR: j, jal, bc1t and bc1f now charge their delay slot. - IR: a syscall sees every earlier instruction charged, including a branch it's the delay slot of, and is charged once it returns. It used to charge itself first, or, in a delay slot, never. - Interpreter: a skipped likely delay slot costs what the instruction would, as in the IR cores, instead of 1. - Interpreter: both run loops go on to the end of what the IR cores run as a block before checking downcount, and charge each instruction as it runs. The CPUEquivalence fuzzer now compares the cycles up to its terminating syscall. With continueBranches off, the three cores now produce the same trace of syscalls and thread switches, ticks included, over several emulated seconds of commercial games. With it on, the IR cores leave the interpreter within a few hundred syscalls, as it moves block ends. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>